( ESNUG 230 Item 1 ) ---------------------------------------------- [11/16/95]
Subject: Pro & Con Altera HDL (was "ESNUG 229 #1 Is Syn DW PCI Worthwhile?")
Chuck Gollnick <chuckg@arnet.com> writes:
>Altera suffers one major problem that caused me to simple pan Altera's PCI
>product: Altera HDL. I've used it in the past and I want it to die. Sorry,
>but the last thing we need is yet another hardware description language.
>Why can't you use Verilog or VHDL like everyone else? Quite frankly, when
>I saw those 4 little letters (AHDL), my response was "Run Away, Run Away."
>Sorry, but that's the truth. Friends don't let friends learn Altera HDL...
From: jacko@altera.com (Jack Ogawa)
John,
Got Chuck's e-mail on PCI; looks like he's been spending some time looking
at many of the solutions that are on the market.
AHDL: Ok, I hear his opinion. But, as you might imagine, there is a
real reason why we didn't do a VHDL version. Let's look at the problem
in terms of functionality, and then optimization.
As a designer, I would imagine that you would focus on the functionality
of your system first. In fact, your first task in an ideal approach to
designing with an HDL is to complete a functional, synthesizable
description, which would be put against a test bench. Subsequently,
then, the task of optimization for the target silicon would begin.
As far as re-usability of a functional description, any well-written piece
of VHDL or Verilog should be functionally compatible with various silicon
targets (including ASICs). The question here is the optimization.
So, what's the problem with VHDL? The problem here is that while VHDL
(or Verilog) is great for describing the functionality of a design, it
is poor for describing specifc logic structures which have been optimized
for a given piece of silicon. So, what's the answer? Well, it would seem
to me that you could instantiate a PCI interface into your overall HDL
design, and then plug in topologies which have been optimized for your
target silicon. In this case, the topology is described in Altera HDL.
In fact, this is the model that LSI Logic has been pushing for several years.
Buy a core from them, instantiate it in your system level description,
and let them provide you with an optimal topology.
Now, there is really one hole which we are trying to address: behavioral
descriptions of the interface so that you can functionally simulate. Oh, I
guess you would argue there are 2 holes -- the additional one being that if
you wanted to change the functionality of the interface, you would have to
modify the Altera HDL.
So, our motivation was to provide functionality described in a language which
allowed us the power to optimize FPGA's. I believe that once we get some
behavioral code in place, that Altera HDL will be a complete solution.
By the way, our implementation easily meets the 33 MHz PCI spec, as well
as the 7ns set-ups and the 11ns clock-to-outputs.
- Jack Ogawa
Altera
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From: [ No, I'm Not A PCI Consultant ]
John, please don't include my name in this article if you decide to print it.
You wouldn't believe the hassels I have to go through to get permission to
put my name on any printed article in my company.
We recently completed a PCI design using an Altera PLD, and ran into a number
of problems. I first wrote the entire code in Verilog and compiled it using
Synopsys, and the resultant netlist only ran at about 10 MHz. It took
extensive hand tweeking and writing many parts of it in Altera HDL before we
finally got the final design to run about 33 MHz, which was our target. The
Altera part (series 8000) certainly can run that fast, but the software can
not take advantage of its speed without manually forcing the place and router
to use the internal cascade paths. Altera and Synopsys could fix this with
a major software revision, but that would take time and money, so don't hold
your breath.
By the way, we inserted the part in a P.C. board and plugged it into a PCI
slot, and after 4 weeks of debugging, the board actually worked! For anyone
who casually thinks they can read the literature about the PCI bus and whip
up a design and debug it in a month or two, they are going to be sadly
mistaken. Plan on at least 4-6 months for your first design cycle. The
learning curve for this bus is very long ("PCI, Hardware and Software" by
Solari & Willse is over 600 pages, and even that doesn't tell you everything
you need to know to design such a board). Hiring a consultant who has
successfully done at least one PCI design would be a very smart idea.
- [ No, I'm Not A PCI Consultant ]
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