( ESNUG 229 Item 3 ) ---------------------------------------------- [11/3/95]
From: puneet@qcktrn.com (Puneet Jethalia)
Subject: Dc_shell Does Verilog & VHDL Yet Fails To Output EDIF
Hi, John,
I've been trying to generate an EDIF netlist from the Synopsys' design
compiler. But there seems to be something missing, as a result of which I'm
getting a "write failed" when I try to generate edif netlist. Verilog or
VHDL netlists come out fine for the same design. A sample session:
dc_shell> write -format vhdl -output syn_out
Information: Writing synthetic library implementations for design
'process1'. Use "write -no_implicit" to get just the design. (UID-172)
1
dc_shell> write -format edif -output syn_out
Information: Writing synthetic library implementations for design
'process1'. Use "write -no_implicit" to get just the design. (UID-172)
Warning: Some designs have no schematic. (EDFO-1)
Designs without schematics: process1_DW01_add_32_1 process1_DW01_add_32_0
process1
Nothing done.
Error: Write command failed. (UID-25)
0
What's going on here and what is it's workaround?
- Puneet Jethalia
Quickturn
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