( ESNUG 229 Item 2 ) ---------------------------------------------- [11/3/95]
Subject: (ESNUG 228 #10) "Is The Synopsys Floorplan Manager Worth Its Price?"
> I would be very interested in hearing from people that have real-life
> hands-on experience with the Synopsys Floorplan Manager. For example, does
> it really do something that I can't do myself by tweaking the constraints &
> process by which I use the dc_shell? If so, under what circumstances would
> this extra something be worth the extra something Synopsys is asking for it?
From: Zia Khan @ Intel
Hi John, I thought I'd put in my $0.02 worth.
First, Floorplan Manager (FM) is an incorrectly named product. It does not
floor plan as one might expect. It is an interface between Synopsys and a
REAL floor planner or P&R engine. Now, about it uses.
1. Most ASIC vendor's libraries provide a set of wire load models that are
grossly inaccurate (or have huge margins built in). If you design to
these targets you will be very hard pressed to meet your timing goals for
high frequency designs.
We use the FM for generating custom wire load models after a trial layout
to get a good wire load model. This helps us fine tune the synthesis
results for a better pre- and post- layout (actual layout for sign off)
correlation.
Our experience has been that (for various reasons) the models in vendor
libraries are up to 200+% inaccurate. With FM generated models you can
come within 25% of actuals. Using custom models helps reduce post-layout
surprises and design iterations.
2. The PDEF interface is a useful feature that allows you to have different
physical and logical hierarchies. So far have not have a need to use it.
I would like to point out that, in my opinion, the wire load calculation
algorithm used by FM has one flaw. When computing wire load models for
higher level design units (major blocks of the chip) the tool incorrectly
includes all net that exist at lower levels of hierarchy thus giving a much
more optimistic estimate (lower than actual) than the real capacitances. I
have found it to be over 200% off for nets that exist at top level of a chip
(nets interconnecting large blocks). BTW, we have communicated this issue to
Synopsys who do not this is a flaw & therefore are not motivated to fix it.
- Zia Khan
Intel Corp.
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