( ESNUG 228 Item 8 ) ---------------------------------------------- [10/20/95]
From: jumana@tcs.com (Jumana Muwafi)
Subject: Lib Compiler Can't Model Clk & Scanclk Yet Test Compiler Needs It
Hi John,
Apparently Synopsys has a problem in modeling the scan equivalent of an
edge-triggered flip-flop using the clocked-scan methodology.
The problem rises from the fact that to model the next state of the register
you need to specify two clocks: the normal operation clock, and the scan
clock, which the Synopsys Library Compiler cannot do. Synopsys says that
in this case the Test Compiler *assumes* the operation of the flip-flop
during scan and operates based on that assumption. The risk is that if the
cell ends up behaving differently from the assumption there is no way to
test it. Any insight into how much of a risk is using this type of test
methodology going to introduce would be greatly appreciated.
- Jumana Muwafi
TCSI
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