( ESNUG 228 Item 2 ) ---------------------------------------------- [10/20/95]
Subject: (ESNUG 221 #2 227 #3) "Non-Linear Libs, Weird Delays & Clock Drives"
> Setting a drive on a clock port has problems. With an "ideal" clock you
> get 0 ns propagation delay and thus the drive strength is ignored, however
> you *will* get a transition delay. This transition delay will be *huge*
> because the load on the clock is large. Creating weird large delays!
From: jaym@hpcvcdt.cv.hp.com (Jay McDougal)
Hi John,
If you have access to a copy of Library_Compiler, here is one workaround for
the problem of transition delay on "ideal" clock networks.
You create a special cell in your synopsys lib that has a fixed transition
delay for all load and input slope cases. This fixed value is simply the
expected transition delay you will get from your clock buffering scheme.
You can also include the intrinsic delay of your clocking scheme as a fixed
Intrinsic Delay. This will model your complete clock buffer with a single
cell (except for skew which can be handled separately.) Using this new cell,
it does not matter what your input drive is set to. The "fake" cell should
be replaced by the actual clock tree during place and route.
- Jay McDougal
Hewlett Packard
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