( ESNUG 226 Item 2 ) ---------------------------------------------- [8/31/95]
From: michael@canada.lsil.com (Michael Smith)
Subject: (ESNUG 225 #3) Surprising Answer To A Personal Metastability Quest
John: For discussion purposes, I'm duplicating Bob's circuit below:
> Dual-Stage Design:
> _____ ------
> / \--------|D Q|
> ------ ------ SYNC | | | |
> ASYNC ----|D Q|----|D Q|-------| Blob | | | Target
> | | | | / of \ ---|> | Flip-Flop #1
> | | | | | logic | | ------
> --|> | --|> | \_ | | ------
> | ------ | ------ \ |------|D Q|
> | | \____/ | | |
> | | | | | Target
> 40MHZ -------------------------------------------|> | Flip-Flop #2
> ------
>
>
> Single-Stage Design:
> _____ ------
> / \--------|D Q|
> ------ SYNC | | | |
> ASYNC ----|D Q|--------| Blob | | | Target
> | | / of \ ---|> | Flip-Flop #1
> | | | logic | | ------
> --|> | \_ | | ------
> | ------ \ |------|D Q|
> | \____/ | | |
> | | | | Target
> 20MHZ ----------------------------------|> | Flip-Flop #2
> ------
In his discussion on why a single-stage design is a better solution, Bob does
say that the delays in the "Blob of logic" should be made as small as
possible. The value of Tblob, the propogation delay through the "Blob of
logic", will lower the value of Tr which may make the dual-stage design more
attractive. There are a few additional points that also should be considered.
In the dual-stage design, if the output from the first flip-flop goes
metastable, there is only a single signal in the design that is metastable.
In the second design, the entire "Blob of logic" is potentially metastable,
-this will effect your power consumption (although marginally.) A bigger
concern is that in the single-stage design, there is a potentially metastable
signal that is being sampled by multiple flip-flops; this makes design
changes and analysis much more difficult. For example, when determining the
value of Tr, the clocking scheme and clock skew between the two flip-flops,
as well as routing delays and differences in the logic paths may have to be
considered. This might lead to problems such as shown in the following:
T1 T2 T3 T4
Clock: ____----____----_____----____----____
ASYNC: ___________--------------------------
SYNC: ____________xxxxxxx__---------------- <- Metstable
D1: _________________xxxxxxx__----------- <- Metstable
D2: ______________xxxxxxx__-------------- <- Metstable
Q1: _____________________xxxxxxxx-------- <- Unknown Value
Q2: _____________________________--------
In this figure, 'D1' and 'Q1' are the D/Q signals for the first target
flip-flop, while 'D2' and 'Q2' are the D/Q signals for the second target
flip-flop. I'm assuming that the "Blob of logic" is just a propogation
delay for this example. I'm also assuming that the first flip-flop settles
to '0' after going metastable, and then properly samples the '1' input on
the subsequent clock edge (T3).
With this example, the two outputs, Q1 and Q2 are different for clock period
T3. Remember that for real gates, 'x' doesn't exist, there will be a '1' or
a '0' on Q1. Some hand-shake or control schemes will fail at this point.
However, if a dual clock stage is used with half the clock period:
T1 T2 T3 T4
Clock: _--__--__--__--__--__--__--__--__--__
ASYNC: ___________--------------------------
ASYNC': _____________xxxx-------------------- <- Metastable
SYNC: _________________xxxx---------------- <- Unknown Value
D1: ____________________xxxx------------- <- Unknown Value
D2: _________________xxxx---------------- <- Unknown Value
Q1: _____________________xxxx------------ <- Unknown Value
Q2: _____________________xxxx------------ <- Unknown Value
In this second case, ASYNC' is the node between the two synchronization
flip-flops. For this scenario, the potentially metastable signal is only
being sampled by a single flip-flop; the output of this flip-flop is a
stable, albeit an unknown value (of course, it is possible for the second
flip-flop to also go metastable if the settling time is sufficiently large).
The result is that Q1 and Q2, although having a value of 'x', they still
have the same value throughout this example. This reduces the number of
possible failure modes of your design, which will make it more robust.
- Michael Smith
LSI Logic (Canada)
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