( ESNUG 225 Item 2 ) ---------------------------------------------- [8/24/95]
Subject: ( ESNUG 224 #5 ) Miracle Healing Of EDIF "write" Problem
>I faced a problem with the Synopsys 3.2b while I am writing out a design in
>EDIF. I read a design in EDIF and selected a cell in it. I executed the
>"link" command and later I tried to save the design with a different name in
>EDIF (using the write command). I got an error saying the "write" failed.
>After selecting the design and executing the link command, I looked at the
>gate level netlist to see whether there was any problem. I did nothing.
>Next, when I saved the design with some other name & it happily worked. (??)
From: drama@india.ti.com (D Ramanath)
Hi John,
This is actually not a bug. The design has to be mapped to gates before
writing out the EDIF design. It is a requirement of Synopsys for EDIF, PLA
and MENTOR formats. (But there is no such requirement with Verilog, VHDL and
db formats.)
- D. Ramanath
Texas Instruments
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