( ESNUG 225 Item 1 ) ---------------------------------------------- [8/24/95]
From: johara@ATVL.Research.Panasonic.COM (Joe O'Hara)
Subject: Synopsys Point-To-Point Timing Exceptions
Hi John,
Here's another contribution to the list of Reasons Why Synopsys (insert
your favorite expletive): If you have a design with point-to-point timing
exceptions (i.e. multicycle paths, false paths), these exceptions become
invisible to the timing analyzer when the design is incorporated into the
next higher level of hierarchy.
I have a design in which several lower level modules contain literally
hundreds of point to point exceptions (mostly from a microprocessor test port
to places in a state machine which are actually inacessible during system
operation.) After I carefully set these up & compile the block until I get
a clean timing report, I set dont_touch on the module and then work on the
next level up. But the timing analyzer does not take the subdesign's
exceptions into account!!! Consequently, I get ridiculous compile times and
a lot of bogus timing violations.
The only solution I am aware of is to write_script from the lower level
design, and then edit all of the -from's and -to's to reflect the cell name
(U-number) of the design in the higher level. <Ugh!> Doing this in a large
design with several levels of hierarchy is obviously a tedious and error
prone process. (Do you know of any more clever ways to overcome this? I am
wary of using the "-hierarchy" switch in the "find()" command as a way of
getting out of typing in the full path to an endpoint -- too much chance for
hitting the wrong one in a large design (plus it doesn't seem to work once
the design has been flattened using "ungroup.")
- Joe O'Hara
Panasonic
|
|
