( ESNUG 224 Item 3 ) ---------------------------------------------- [8/8/95]
Subject: (ESNUG 222 #1 223 #2) Verilog Parsers, full_case, parallel_case 3.3a
>Personally, I hate the new Synopsys Verilog 3.3a parser. With the following:
>
> always@ (A0 or M)
> case (A0) // synopsys full_case
> 3'b 000 : z0 = 0;
> 3'b 001 : z0 = M[0];
> 3'b 010 : z0 = M[1];
> 3'b 100 : z0 = M[2];
> default : z0 = 1'bX;
> endcase
>
>It has a "default" statement therefore it is complete by definition -- yet I
>get the following message:
>
> Warning: You are using the \fBfull_case\fP directivewith a case
> statement in which not all cases are covered. (HDL-370)
>
>What is "\fBfull_case\fP" ?? Not all cases covered?? It has a "default"!
> (Fortunately, the resulting logic seems correct.)
From: [ No Muck Please ]
John, (anonymity, please, I just wanted to follow-up on this)
The warnings from the 3.3a Verilog reader (via the "full_case" and
"parallel_case" compiler directives) are wrong. According to Synopsys, they
can safely be ignored (assuming the case statements are indeed full/parallel).
- [ No Muck Please ]
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