( ESNUG 223 Item 3 ) ---------------------------------------------- [7/26/95]
From: jcooley@world.std.com (John Cooley)
Subject: Can't Use Multiple Verilog "Always" Or VHDL "Process" Loops w/3.3a
My sources in Synopsys just told me that Design Compiler 3.3a may *fatal*
when encountering a Verilog reg or a VHDL signal in more than one of their
respective always/process loops if it infers either registers or latches.
(It fatals with error id=591124 in v3.3a.) The two workarounds are:
- Before compiling set a switch that defaults back to v3.0b with:
hdlin_seq_device_v30_mode = "true"
- or -
- Edit your Verilog/VHDL source code to contain only one "always" per
"module" or one "process" loop per "architecture."
In my opinion this is *basic* functionality of a synthesis tool. This tells
me that if you can avoid using v3.3a, do so!
- John Cooley
the ESNUG guy
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