( ESNUG 222 Item 6 ) ---------------------------------------------- [7/21/95]
From: jtran@ATVL.Research.Panasonic.COM (Jimmy Tran)
Subject: How To Code Verilog & VHDL For Neg Edge Flip-Flops?
Hi John,
I have to raise some old questions again, and hope that you can help me to
put this issue to bed for good (I don't want to see it come back in any
future revision of DC Compiler!)
I have a design that mostly uses pos edge clock. However, I also need to
have couple neg edge flip-flops. V3.2b always gave me random circuitry.
Sometimes, I get an inverter on a clock line (which I don't want it),
sometimes I get a correct neg edge FF inferred (thank God !)
I went back to some of the ESNUG articles (ESNUG-151). People recommended
attribute "neg_edge_flip_flop_opt". However, I could not find any info
related to this attribute from Synopsys OnLine Doc V3.2b(?) Could you help
me to clarify this issue ? What's the best way to code for neg edge FF's?
- Jim Tran
Panasonic Advanced Television Video Laboratories, Inc.
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