( ESNUG 222 Item 5 ) ---------------------------------------------- [7/21/95]
From: [ Nihongo-Man ]
Subject: JK Flip-Flop Synthesizes Only With Bad Verilog
Hello John, Please keep this anonymous.
I've a question about synthesizing JK Flip-Flop with Design Compiler. I
can't synthesize appropriate circuit with following Verilog description.
module jkff(j, k, q, ck);
input j,k,ck;
output q;
reg q;
always @(posedge ck) begin
case( {j, k} )
2'b01: q = 1'b0; // Reset
2'b10: q = 1'b1; // Set
2'b11: q = ~q; // Toggle
2'b00: q = q; // Hold
endcase
end
endmodule
The result of this can't remove 'X' until Reset Condition. But deleting Hold
Condition ( 2'b00: q = q ), the result seems good. (?) I'd like to know what
difference of algorithm whether writing Hold Condition or not, in 'case'
statement. I'm using synopsys ver3.0c
- [ Nihongo Man ]
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