( ESNUG 222 Item 2 ) ---------------------------------------------- [7/21/95]
From: kurt@wsfdb.com (Kurt Baty)
Subject: 3.2b Lame Verilog To VHDL Translation Even With Bug Fix
John,
As you know, a lot of people use Design Compiler as one of the world's most
expensive Verilog to VHDL translators at times. Doing this, I found:
module test(ins,outs);
parameter width = 8;
input [width-1:0] ins;
output [width-1:0] outs;
wire [width-1:0] outs;
assign outs = ins;
endmodule
Translated into VHDL as
library IEEE; use IEEE.std_logic_1164.all;
package CONV_PACK_test is
type typeId_0 is array (7 downto 0) of std_logic;
type typeId_1 is array (7 downto 0) of std_logic;
end CONV_PACK_test;
library IEEE; use IEEE.std_logic_1164.all;
use work.CONV_PACK_test.all;
entity test is
generic( width : INTEGER:=8);
port( ins : in typeId_0; outs : out typeId_1);
end test;
architecture SYN_verilog of test is
begin
outs <= ( ins(7), ins(6), ins(5), ins(4), ins(3),
ins(2), ins(1), ins(0) );
end SYN_verilog;
When I try to hook this up to anything else, the weird "type typeId_0 is
array (7 downto 0) of std_logic;" is BAD NEWS. By setting:
dc_shell>vhdlout_single_bit = VECTOR
I now get an improved:
library IEEE; use IEEE.std_logic_1164.all;
entity test is
generic( width : INTEGER:=8);
port( ins : in std_logic_vector (0 to 7);
outs : out std_logic_vector (0 to 7));
end test;
architecture SYN_verilog of test is
begin
outs <= ( ins(0), ins(1), ins(2), ins(3), ins(4),
ins(5), ins(6), ins(7) );
end SYN_verilog;
Which used the correct type (std_logic_vector) but the original Verilog [7:0]
bit order has been replaced by a reversed VHDL (0 to 7) bit order! Ugh!
- Kurt Baty
WSFDB Consulting
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