( ESNUG 222 Item 1 ) ---------------------------------------------- [7/21/95]
From: fiedler@nvidia.com (Larry Fiedler)
Subject: A Collection Of Five 3.3a Fatals
John,
We got bit by one 3.3a bug which results from unmapped logic being timed.
This happened by having a Flip-flop in a previous technology that had
a reset and clear but in the next technology there are reset *or* clear,
but not *both* types of flip-flops. This caused unimplemented logic in
synthesis which caused a fatal during timing.
There was also a 3.3a bug which had to do with reading a variable in two
Verilog "always" blocks.
Personally, I hate the new Synopsys Verilog 3.3a parser. With the following:
always@ (A0 or M)
case (A0) // synopsys full_case
3'b 000 : z0 = 0;
3'b 001 : z0 = M[0];
3'b 010 : z0 = M[1];
3'b 100 : z0 = M[2];
default : z0 = 1'bX;
endcase
It has a "default" statement therefore it is complete by definition -- yet I
get the following message:
Warning: You are using the \fBfull_case\fP directivewith a case
statement in which not all cases are covered. (HDL-370)
What is "\fBfull_case\fP" ?? Not all cases covered??? It has a "default"!
(Fortunately, the resulting logic seems correct.)
There's also a 3.3a bug that has to do with using a Verilog parameter as an
index to a vector.
parameter N = 3;
zn = Z[N];
the error being: "Error: Untyped variable 'N' used" -- huh?
The supposed solutions is to use a pre-3.3a reader or to change the source
code. This makes me mad! It parsed well before, its very standard Verilog
not esoteric at all, and now it doesn't parse! I hope this gets fixed for
3.3b. Could I encourage proper Verilog parameter handling with "defparam"
at the same time? I know I won't get this, but I ask at SNUG every year.
(Besides, if they fix it, then what will I get to complain about?)
After all of this my collegue is still getting an unknown 3.3a fatal during
the optimization stage.
- Larry Fiedler
NVidia
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