( ESNUG 221 Item 3 ) ---------------------------------------------- [7/13/95]
Subject: (ESNUG 220 #1) Weird Asynch Pins In Xilinx VSS Library
>I found it odd that there are 2 asynchronous pins each: GSR & CLR for cell
>FDCE, GSR & PRE for cell FDPE in the Xilinx xc4000_FTGS.vhd of XACT5.1 for
>simulation of VSS. Has anyone found problems with these cells?
From: mjm@hpqt0326.sqf.hp.com (Murdo McKissock)
Dear John, I've that problem too. It's nice to know I'm not alone!
I have not succeeded in using the VSS simulation libraries for synthesis,
because the Xilinx synthesis libraries omit the GSR pin. For now I'm using
liban to build separate Xilinx VHDL libraries for synthesis only.
Unsatisfactory as it means editing the VHDL RTL code between simulation and
synthesis. (Personally, I like the 2 asynchronous pins. After all this is
how the cell behaves.) The Xilinx documentation assumes users will leave
global reset out of the RTL code, but I for one need to include it in
pre-synthesis VHDL code.
There should be a single VHDL package which provides synthesizable component
declarations for all the Xilinx library components as well as simulation-only
models bracketed with translate_off directives. That may require adding the
GSR pin to the FPGA compiler synthesis libraries ...
- Murdo McKissock
Hewlett-Packard Scotland
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From: steve.sharp@xilinx.com (Steve Sharp)
Hi John,
The answer to this quite resonable question lies in the internal structure
of the Xilinx XC4000 devices. These devices have a "hidden" net called
"GSR" (Global Set/Reset) that connects to every flip flop in the device
(even I/O block flip flops). The GSR net is asserted on power-up, plus a
user can connect any chosen signal to it as well. This GSR connection is
made by instantiating a STARTUP symbol and connecting it's "GSR" pin to
the desired global reset signal. (In the v3.2 Xilinx Synopsys Interface
libraries you need to set a "dont_touch" attribute on the instantiated
STARTUP to prevent the compile process from removing it. In the v3.3 XSI
libraires the dont_touch attribute is already present on the STARTUP cell).
Using the GSR net allows local (often high fanout) connections to the CLR
or PRE pins to be removed, thereby freeing up a significant amount of
local routing resources. When the XNFPREP program detects local CLR or PRE
connections also connected to the GSR pin of a STARTUP symbol, it removes
the local connections since they are redundant.
Since the GSR net is not available to the synthesis tools, there are no GSR
connections in the synthesis library (just CLR or PRE pins as appropriate.)
The VSS simulation libraires have both asynchronous pins because there will
be connections to both after place and route.
The XNF2VSS back annotation program will add a net called "GSR" to the
post-route netlist if the user does not use a STARTUP symbol to specify which
signal should be connected to the internal GSR net in the chip. This port
should be toggled (active high) at the beginning of the simulation to get
all registers into their power-up state. If the user did use STARTUP to
specify a GSR connection, that signal will be connected to the GSR pins of
all flip flop cells in the post-route netlist.
Local reset or preset behavoir of selected subsets of registers can still
be specified in the code behavior and will be synthesized using the local
CLR or PRE pins on the specified registers. (Just remember that the GSR
net resets or sets EVERY register in the chip).
Note: for XC5200 designs, the same concept applies except that the registers
only have CLR connections and the internal global signal is called "GR" (for
Global Reset). Likewise, the STARTUP cell has a GR pin instead of GSR.
Using the GSR net where possible can improve routability of Xilinx XC4000
(and XC5200) designs. We encourage users to take advantage of it.
- Steve Sharp
Xilinx, Inc.
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