( ESNUG 221 Item 2 ) ---------------------------------------------- [7/13/95]
Subject: (ESNUG 220 #5) Size Dependant Hierarchical Timing Bug (3.1b & 3.2b)
>I have timing report from a design, showing a 44.12ns path. I move up a
>level in the hierarchy, so the previous design is now an instance named
>"cntl" in this upper design. Now the *same* path now shows 214.02ns delay!
>It appears that this bug *only* occurs if you have a non-default driver on
>your input ports (i.e., if you leave it with the default "infinite" drivers,
>everything works). It doesn't matter if the path uses the clock or not.
From: sgolson@trilobyte.com (Steve Golson)
Further developments show this has nothing to do with hierarchical designs.
I see the problem on a single design. Run report_timing and see a path with
20ns delay, then put a non-inifinite drive on the clock pin with
"set_driving_cell" and report_timing shows 210ns delay.
- Steve Golson
Trilobyte Systems
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