( ESNUG 220 Item 1 ) ---------------------------------------------- [7/7/95]

From: linjeff@tk0.taisel.alcatel.com.tw (Jeff Lin)
Subject: Weird Asynch Pins In Xilinx VSS Library

Dear John,

I found it odd that there are 2 asynchronous pins each: GSR & CLR for cell
FDCE, GSR & PRE for cell FDPE in the Xilinx xc4000_FTGS.vhd of XACT5.1 for
simulation of VSS.  Has anyone found problems with these cells?

  - Jeffrey Lin
    Alcatel
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