( ESNUG 215 Item 4 ) ---------------------------------------------- [4/20/95]
Subject: (ESNUG 213 #4) Model Tech/Synopsys VHDL Simulator Incompatibilities
>Has anyone had experience with incompatabilities between VSS (Synopsys)
>and VSIM (Model Technology)?
>
>We developed a VHDL model in Model Tech's VSIM and completely debugged it.
>When we ran the same model in Synopsys's VSS, we found that 20 out of 96 test
>sets had some sort of miscompare. I'm not surprised that different vendors
>evaluate the VHDL language differently, but I'm surprised how difficult it is
>find references detailing these differences. Any help will be appreciated.
From: matt_hsu@mhsu.com (Matt Hsu)
Hi John,
I've had experience supporting both of these VHDL simulators as I was
responsible for building the system simulation environment at my last
company (as well as a third simulator for a while).
Basically, most of the VHDL simulators I've come in contact with (either
evaluating or using) are either generally the same or too non-compliant to
mention (and most of those have died). We used to used a regression testing
philosophy that was based on 'diff'-ing golden response files but came across
the following two problems that may address this user's particular experience:
1) When using textio and the NOW function to output time stamps I found
that different simulators would use different default units. Although the
time write function allows you to pick a unit, it doesn't specify whether
the unit should be printed in upper or lower case and guess what? We saw
both. (Yes I kow you can work around case 'diff'-ing.) Trying to convert
to an integer (so 'ns' could be a string) was even more trouble because
when I divided by 1 ns, for example, I got different answers. I'm guessing
because some of the simulators wanted to give more dynamic range by
cutting range off of the bottom half of the physical definition & putting
it on the top (using a sliding scale for where integer 0 is). I couldn't
find a formula to give me the same integer for all three simulators.
2) Even more troublesome was the fact that a list of simultaneous events
would be ordered one way in one simulator and another in the other. The
following example illustrates the problem. Suppose you have a signal that
is two bits wide. You write two processes each having one bit in the
sensitivity list. In each process, you print out the new value for the bit
when the signal changes. Now, which text comes out first: the 'left bit
text or the 'right? I saw both making the 'diff' output too long to be
convenient.
For this reason we wrote a reduction and analysis script that would tell us
the whether the test passed or failed. In my opinion, the better way we
implemented later was to have the testbench check and generate a "PASS"
message when the test passed and status output for debugging when it
failed. Using this technique we built into our designs assertion warning
process that were quiet when all was well and yelled out if they detected
problems. Synthesis of these warnings was disabled.
- Matt Hsu
Ryan & Ryan
|
|
