( ESNUG 214 Item 4 ) ---------------------------------------------- [4/14/95]
From: rray@poci.amis.com (Russell L. Ray)
Subject: VHDL Full Timing Gate Simulation (FTGS) & Support Center Problems
John,
I'm wondering if anyone else is having problems modeling with FTGS & getting
support from the support center. An FTGS (Full Timing Gate Simulation)
model is the VSS accelerated VHDL model. It is desirable to use these models
over other VHDL models because Synopsys has optimized the packages into the
kernel to improve simulation speed. I have several cells that are
"complex" combinational gates. One in particular has the boolean function
Q = (A and B) nor (C and D). I want to have glitch detection & x-generation
enabled so that when the inputs change to close to each other, I get a
warning and an X injected into the simulation.
My case is this: B='1', D='0' and have for a long time. A rises from '0' to
'1' soon (~5 ps) after C falls from '1' to '0'. Since D has been '0' for a
long time, the C path should be "disabled". However, the FTGS model reports
a glitch and I get an X out. I have tried several times to get responses
from the support center on this one but I seem to have found a "black hole".
(Generally I'm pleased with the support center, but this case is not it.)
- Russell L. Ray
American Microsystems, Inc.
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