( ESNUG 214 Item 3 ) ---------------------------------------------- [4/14/95]
Subject: (ESNUG 213 #1) "DC 3.2a vs. 3.0b -- Smaller But Slower Designs?"
> Design Compiler 3.0b Design Compiler 3.2a
> -------------------- --------------------
> Combinational area: 39,936.000 38,893.750
> Noncombinational area: 27,637.250 27,714.250
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got larger noncomb area here ---'
From: [ Noisemaker ]
Hi John,
(I don't know if you remember me; you told me that I'm an obvious "Noisemaker"
after a SNUG '95 breakout session... <grin> Anyway don't show my name or CO.)
I have a little problem with the above results, and that's basically the
noncomb logic area has increased. More info is needed here to explain this
increase: is it because Synopsys simply synthesized different cells (i.e.
buffered FF, etc... ) -- or is it because there are unknown additional FF
and/or latches??? I've encountered a few cases where the same HDL code and
scripts synthesized differently. In one specific case between Synopsys v3.0c
and v3.1b, we ended up with extra latches in 3.1b. We traced the source
of the problem to the actual HDL which indeed inferred latches but the
latch's Gate pin was tied high in one level up in the hierarchy with
set_logic_one (i.e. the latch is in pass through mode. This is a no-no I
know, nevertheless it happened) Both versions synthesized the correct logic;
but one with larger area.
My point is DON'T ALWAYS BLAME THE TOOL FOR DISCREPENCIES YOU GET, RATHER
TREAT IT AS MORE INFORMATION ABOUT YOUR DESIGN AND FIND OUT WHY THE RESULTS
ARE DIFFERENT. This can be very annoying and source of headache but it's got
to be done. (This is especially true in design re-use with HDL code written
and modified by previous peers over and over again.)
- [ Noisemaker ]
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