( ESNUG 213 Item 6 ) ---------------------------------------------- [4/5/95]
Subject: (ESNUG 211 #5) Use set_max_fanout With Much Caution!
>USE CAUTION WITH SET_MAX_FANOUT ON THE ENTIRE DESIGN! Our methodology used
>to have as part of the process a "set_max_fanout = 10" on the entire design.
>This caused timing problems on our modules which drove the outputs of the
>ASIC. ... Design Compiler correctly used the largest buffers available
>(BUFF3 - which had a fanin of 3 inputs attributed to their inputs). The
>set_max_fanout caused Synopsys to only drive 3 BUFF3's with a single BUFF3,
>and the worst path for these outputs was a string of three BUFF3's in a row.
> ... Design Compiler gave a mish-mash 3 layer buffer tree when it could
>have built a nice balanced 2 layer buffer tree... We later found that
>set_max_transition, used correctly was the command to use instead.
From: [ The Synopsys CAE for Design Compiler ]
This is a frequently encountered design methodology problem. As the user
determined, max_fanout can be a potentially dangerous design rule to apply
to an entire design. If it is desirable for the design to have a
"set_max_fanout = 10" except for the BUFF3 (and similar cells), a two pass
methodology could be used.
On the first pass, apply either no design rule constraints (max_fanout or
max_transition) or a loose design rule constraint and compile the design.
If the synthesis library has design rule constraints on the cells these
will be followed during this pass.
On the second pass, dont_touch all the BUFF3 (and similar cells) that you
don't want the more restrictive "set_max_fanout" or "set_max_transition"
constraint to affect. Compile as before and the tighter design rule
constraint will be applied but leaving the dont_touched cells alone.
- [ The Synopsys CAE for Design Compiler ]
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