( ESNUG 213 Item 1 ) ---------------------------------------------- [4/5/95]
From: prz@hprnd.rose.hp.com (Paul Zimmer)
Subject: Design Compiler 3.2a vs. 3.0b -- Makes Smaller But Slower Designs?
John,
I've heard rumblings that 3.2a seems to produce larger, slower designs than
3.0b. So, I completely re-synthesized a chip we released with 3.0b and 3.2a.
Except for the Test Compiler stuff, no changes were necessary in any of the
source files. Test Compiler seems to have arbitrarily changed things like
the default number of scan chains (it now creates one per clock?), and the
default test port names. A recent post (ESNUG 213 #3) from "Jan Decaluwe"
indicates that this is an improvement. Still, it took some struggling to
find and fix all these things, but I finally got some results:
Design Compiler 3.0b Design Compiler 3.2a
-------------------- --------------------
Combinational area: 39,936.000 38,893.750
Noncombinational area: 27,637.250 27,714.250
Net Interconnect area: 146,492.625 146,057.188
Total area: 214,065.875 212,665.188
Path Group A's slack: 8.18 8.17
Path Group B's slack: ***? -3.96
Path Group C's slack: -1.58 -2.05
Path Group D's slack: 4.44 7.17
Path Group E's slack: -1.22 -3.34
(Remember that the more positive slack is, the better one's
gate level design is meeting the constraints you give it.)
***? - This path group came up in 3.0b but report_constraint -verbose
wouldn't give me any "slack" information. Same script, source,
and constraint files. Very strange.
It appears that 3.2a produced a slightly smaller, but noticably slower,
design overall. That doesn't give me a warm, fuzzy, feeling. Since
the chip was built in parallel on many machines, I don't have a good feel
for compile times.
The library is VLSI's "vsc450" 0.8u std cell, version v3r1.5. As you can see,
they use heavy net area in their wire load models. Some experiments we did
on this same chip showed this to produce better results than either VLSI's old
wire load tables (not too hard) or our in-house, Lee Bradshaw (ESNUG 143 #3)
versions. But that's another story...
As a final note, I wanted to include the results of "report -constraint"
as a tidy overview of the chip, but 3.2a fatals every time I try this...
- Paul Zimmer
Hewlett Packard, Roseville
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