( ESNUG 212 Item 4 ) ---------------------------------------------- [3/9/95]
From: brad@crosscheck.com (Brad Plata)
Subject: Seeking Tools/Scripts To Translate A VSS Library -> Verilog Library
Hi John,
Thanks for doing ESNUG -- it's very useful in keeping me up to date. Thanks.
Since you are the expert in this area, I need some help to convert a VSS
library from Synopsys to a Verilog liberary so we can do some testing for
IDDQ. Is there a tool that can read the VSS library and output the Verilog
models with timing (or without timing I can later add that by hand if I
have to.) I really don't want to do 400 cells by hand. If you can help
that would be great.
- Bradley Plata
CrossCheck Technology
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