( ESNUG 212 Item 3 ) ---------------------------------------------- [3/9/95]
From: jand@easics.be (Jan Decaluwe)
Subject: Test Compiler 3.2a Is Fantastic Compared To Test Compiler 3.0a!
John:
We have used Test Compiler for several years now, and as for many others this
has often been a frustrating experience. However, TC 3.2a has been a pleasant
surprise. Here are some important improvements:
Test insertion
----------------
Our designs typically have multiple clocks; 1 or 2 clocks drive the bulk of
the flip-flops while the other clocks are lightly loaded. Our goals with
test insertion are the following:
* flip-flops from different clocks should be in separate scan chains
* all available chains should be used and balanced as much as possible
TC 3.0c balances chains by default, but flip-flips from different clock
systems are mixed. There is a variable you can set to prevent this, but
in that case TC 3.0c refuses to use all available chains and to balance
within clock systems. You end up with only one (possibly very large)
chain per clock. The workaround involves "manual" chain allocation &
balancing and a lot of overhead work & scripts.
In TC 3.2a, test insertion works as desired (see above) by default !
Clock capture groups
----------------------
Support for clock capture groups is a new feature in TC 3.2a. This concept
prevents timing problems associated with paths between different clock
systems during the evaluation cycle: only one capture group (consisting of
a set of clocks) is active per evaluation cycle. The assignment of clocks
to capture groups is done intelligently by the tool, by taking into account
the relative position of clock edges in the test cycle, and the existing
communication paths (which can be influenced by set_test_isolate commands).
Benchmarking ATPG run time
----------------------------
We have seen a major improvement in ATPG run time with TC 3.2a, especially
on the final runs at the top level. The following table shows ATPG run
times for the final vectors of 4 recent projects.
Design Total # faults ATPG run time TC version Workstation/memory
(non-collapsed) (CPU)
---------------------------------------------------------------------
1 44336 7705.21 sec 3.0c Sparc10 128MB
2 136450 89257.55 sec 3.0c Sparc10 128MB
3 89620 700.57 sec 3.2a Sparc5 128MB
4 229598 5614.07 sec 3.2a Sparc5 128MB
All designs had multiple clock systems, RAMs, & some hard-to-test circuitry,
and achieve a fault coverage in the range of 93-96% for the core logic. I'd
recommend jumping to TC 3.2a if you're not there now.
- Jan Decaluwe
Easics, Belgium
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