( ESNUG 211 Item 6 ) ---------------------------------------------- [3/2/95]
From: menne@pasta.enet.dec.com (Mike Minne)
Subject: Dissimular Libs Affecting ASIC to FPGA Technology Translation?
John,
I have a design that was originally entered schematically with Viewlogic and
was translated by Synopsys from a Toshiba 1.0 micron library to VTI653 ASIC
technology.
I want to hardware emulate it in large Altera or Xilinx FPGA's. How can I do
a Synopsys technology translation between such dissimilar libraries ? (The
goal is to get hardware emulation working, then begin coding the hierarchical
blocks into Verilog HDL, and synthesize and emulate until we have a completely
architecture independent Verilog design.)
- Mike Menne
Digital Equipment Corp.
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