( ESNUG 211 Item 4 ) ---------------------------------------------- [3/2/95]
From: lfchao@cpre1.ee.iastate.edu (Liang-Fang Chao)
Subject: Two Newbie Design Compiler and Design analyzer Questions
John, we're new to HDL's and synthesis. Using Synopsys's Design Compiler
and Analyzer I have the following questions:
1. In Design Analyzer, how do you find a realistic minimum cycle period for
a sequential circuit? (The critical path reported by the tool seems much
too short. I did specify the clock, but the critical path reported is
6.26 nsec when there was a combinational path of over 19 layers.)
2. What is *GEN*167 box in the initial schematic, when I used a "case"
statement. Where can I find descriptions of these generic cells used
by Synopsys tool?
- Liang-Fang Chao
Iowa State University
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