( ESNUG 210 Item 4 ) ---------------------------------------------- [2/24/95]
From: zeisu@snipe.dwe.co.kr (Jae-Soo Yoon)
Subject: Positive Edge Oriented "balance_registers" Creates Poor Designs
John,
I was trying to break down a design block into several pipelined stages using
the balance_registers command. The block is similar to an array multiplier
to which I attached three rows of registers to make it four-stage pipelined.
My whole design basically uses a negative edge clock for the storage elements,
and thus I described the pipeline registers to work at the neg edge w/ WAIT
statements as usual. Once I read in the design and optimized it with low
mapping effort, it, of course, created the original block with three rows of
neg edge F/Fs connected to the output port.
Then I recreated clock with my desired cycle and issued balance_registers
command. What I got after the execution was essentially a pipelined design
with all the F/Fs having *positive* edge clocks! Then I gave it an exact
F/F type attribute and repeated the above procedure. (I noticed that then it
printed "preferred register" as FDN1A, which was the neg edge F/F that I
told it to use.) It then attached an *inverter* to the global clock net and
was still treating the whole design as if using a positive clock!
I looked up every reference I could find to make balance_registers use
negative edge clock, but there are none. Is it a bug or a feature that I'm
missing here? I can't believe a synthesis tool creating an opposite result
from the original user's intention given by the HDL description. Please help.
- Jae-Soo Yoon
Daewoo Electronics Co., Ltd.
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