( ESNUG 210 Item 1 ) ---------------------------------------------- [2/24/95]
Subject: (ESNUG 209 #5) VHDL Errors Using "liban" rev. 5.1d On My FPGA
>Using the Synopsys liban program to extract the xprim_4000_5_components.vhd
>and xprim_4000_5_FTGS.vhd.E files from xprim_4000-5.db library, I got errors
>involving:
> REAL port name: A<0> VHDL port name: Ax0x
>
>I used the following command:
>
> liban -arch FTGS syn/xprim_4000-5.db -output src/xprim_4000_5 -xgen
>
>My question is: How can I tell to liban to use "(" and ")" instead of x
>in the VHDL port name? (I want A(0) instead of Ax0x.)
From: krish@neomagic.com (Krishnan Dharamrajan)
Hello John,
I had this problem. This happens when one has library cells w/ ports defined
as a BUS. While generating the library files these BUSSED ports have to be
bit-blasted and each of these ports are assigned unique timing variables.
IF you have a bus defined as A : std_logic_vectors(7 downto 0);, this will be
blasted as Ax0x, Ax1x, ... Ax7X and not as A(0), A(1), .... A(7), since
port names like A(0), A(1), .... A(7) are not allowed in VHDL.
- Krishnan Dharamrajan
NeoMagic
--- --- --- ---
From: sharp@xilinx.com (Steve Sharp)
From the looks of this question, I suspect the user may be trying to get a
RAM16x1 or RAM32x1 model. He should check out the new rev of the
Xilinx-Synopsys Interface (Xilinx part number DS-401 version 3.2 -- shipped
Jan. 95) It has many updates to the synthesis libraries AND full FTGS models
for VSS for XC3000, XC4000, and XC7000 devices plus back annotation
translation from post-route XNF to VHDL/SDF.
- Steve Sharp
Xilinx
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