( ESNUG 209 Item 7 ) ---------------------------------------------- [2/1/95]

From: jc@lsil.com (Joseph Cesana)
Subject: How To Retain A Verilog Function's Hierarchy After Synthesis?

Hi John, I'd like to know if Synopsys can synthesize a Verilog Function and
keep it as a submodule.  (I know it can synthesize it but the Function is
flattened at the top level.)  Is there any command that would keep the
Function as a hierarchical entity?

  - Joseph Cesana
    LSI Logic
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