( ESNUG 209 Item 5 ) ---------------------------------------------- [2/1/95]
From: gel101@gel.ulaval.ca (Vincent Rowley)
Subject: VHDL Errors Using "liban" rev. 5.1d On My FPGA
Hello, John,
Using the Synopsys liban program to extract the xprim_4000_5_components.vhd
and xprim_4000_5_FTGS.vhd.E files from xprim_4000-5.db library, I got errors
involving:
REAL port name: A<0> VHDL port name: Ax0x
I used the following command:
liban -arch FTGS syn/xprim_4000-5.db -output src/xprim_4000_5 -xgen
My question is: How can I tell to liban to use "(" and ")" instead of x
in the VHDL port name? (I want A(0) instead of Ax0x.)
- Vincent Rowley
Cite Universitaire, Quebec, Canada
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