( ESNUG 208 Item 5 ) ---------------------------------------------- [1/26/95]
From: jackm@synopsys.com (Jack Marshall)
Subject: Seeking Confessions From The Speed Freaks
John,
I'd like to see on ESNUG the techniques people use to get high speed designs
from synthesis. Assume you are starting out with good coding style, good
partitioning for synthesis, and a good synthesis library. Assume the default
compile ("compile") doesn't meet your timing goals. What do you do next?
Map effort high? How do you overcome local minimums? What if that doesn't
work? What do you try next? I would like to see ESNUG answers posted as:
First, I try this ....
Second, If that doesn't work I try ...
Third, If that doesn't work I try ...
I would also like to know "rules of thumb". For example: "If the design
isn't meeting timing by 20% of the clock period I try ... If it is only
missing by 5% - 8%, I try ..."
Also: how often do your techniques work? For example: "default compile works
30% of the time. Map effort High, with -incremental works 80% of the time
based on the 8 ASICs I have designed with Synopsys"
- Jack Marshall
Synopsys - Austin, Texas
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