( ESNUG 207 Item 3 ) ---------------------------------------------- [1/18/95]
Subject: (ESNUG 206 #3) If Reading Flat Verilog Chokes, Try Reading In EDIF!
>John, we've discovered a problem in Synopsys when trying to read in large
>flat Verilog files. In a nutshell, Design Compiler hangs, creates a extra
>large core dump, then exits with a segmentation error or fills the disk up
>while dieing un-gracefully. The problem appears to only happen when
>reading in a flat Verilog file of a full ASIC design.
From: swanson@romulus.cray.com (Gary Swanson)
John, It looks like some defaults were not set large enough for stack size.
The problem was a fatal segmention error & stack overflow. Change the
limits and our problem went away. In csh, for instance, you can check the
max size of the stack by using the UNIX command "limit":
UNIX PROMPT> limit
cputime unlimited
filesize unlimited
datasize unlimited
stacksize 8192 kbytes
coredumpsize unlimited
memoryuse unlimited
descriptors 64
Our stacksize of 8192 kbytes was not sufficient. The solution (in csh) was
to run the UNIX command "limit stacksize unlimited" (or to be safe)
"limit stacksize 100000".
- Gary Swanson
Cray Research
[ Editor's Note: Gary, thanks for following up on your orginal post. - John ]
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