( ESNUG 206 Item 3 ) ---------------------------------------------- [1/13/95]
From: swanson@romulus.cray.com (Gary Swanson)
Subject: If Reading Flat Verilog Chokes, Try Reading In EDIF!
John, we've discovered a problem in Synopsys when trying to read in large
flat Verilog files. In a nutshell, Design Compiler hangs, creates a extra
large core dump, then exits with a segmentation error or fills the disk up
while dieing un-gracefully.
The problem appears to only happen when reading in a flat Verilog file of
a full ASIC design. If you want to read in the flat design, you should read
in the EDIF version of the design. The Verilog files we found this problem
on work correctly with Verilog-XL or any other Verilog tool.
- Gary Swanson
Cray Research
[ Editor's Note: Thanks for the tip. Finding out what rev of Synopsys you're
using & your follow-up to this problem will make interesting ESNUG. -John]
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