( ESNUG 206 Item 2 ) ---------------------------------------------- [1/13/95]
Subject: (ESNUG 205 #5) Headaches Going Synopsys To Mentor Using "db2eddm"
>We have a group within our company that is trying to go from Synopsys
>database (.db files) into Mentor by using their db2eddm product. (When
>we asked both Mentor & Synopsys about going from EDIF to EDDM, the answer
>was a definite "NO".) We have encountered some problems with the db2eddm
>path (nets crossing bus rippers that were shorted in Mentor and not in
>Synopsys, etc.) and find this problem time consuming and cumbersome. Do
>you have any suggestions from any of your ESNUG readers?
From: Sean_Atsatt@notes.seagate.com (Sean Atsatt)
John,
We have been having the same problem with db2eddm although it appears that
Synopsys has partially fixed the problem in later releases. The majority of
the problems we had, were when the translated schematic had a wire
incorrectly shorted to a bus when the wire crossed the bus at a ripper. (This
appears to have been fixed in version 3.0b.) We are still seeing busses
shorted to busses when they cross at a ripper (so far it only seems to happen
on busses that are connected to ports, but that may just be coincidence). We
found no general solution to this problem other than to go in and fix each one
by hand. Luckily there are usually only a couple of these shorts and the
Mentor tool reports them (although it might not if the bus shorts were not on
a port). I'm hoping that Synopsys will do a complete the fix to this problem.
- Sean Atsatt
Seagate
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From: philip@old_zelda.mti.sgi.com (Philip Schmidt)
John,
I also encountered a problem with using busses and rippers. I went from a
Synopsys db file to an EDIF schematic and found out that when the wires
crossed a ripper symbol in Synopsys v3.0b that a short resulted in the
schematic! This was supposed to have been fixed in v3.0c but I decided
to not use rippers and busses by then. Instead I flattened the design prior
to writing it out of Design Compiler and generated the schematics as a flat
design. (This does have a problem in that if you have too many signals at
the top level, you will get a symbol which is way too big for any schematic
page. I use Concept and so I just created a bussed symbol outside of
Synopsys to represent the schematic generated. The I/O signals are connected
by name and thus does not cause a problem.)
- Philip Schmidt
Silicon Graphics
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From: jgais@wd.estec.esa.nl (Jiri Gaisler)
John, I've transferred designs from Synopsys to Mentor using the Mentor
generic netlist editor (Neted), bundled with Autologic. The transfer is
performed in four steps:
1. A EDIF netlist is created in Synopsys (netlist view only)
2. A patch script is run on the netlist to remap cell names, which for some
reason, never seems to be the same in Mentor as in Synopsys.
3. The patched EDIF netlist is read by Neted and written out in Mentor EDDM
4. The schematic generator (Schemgen) and view point editor is run on the
EDDM to create the Mentor schematics and hierarchy.
The process is automatic once the map file for renaming of the cells is
generated. Depending on how the EDIF netlist is generated, some signals
(buses) might change name. I can post the relevant scripts if anybody is
interested. Currently, I have map files for GPS 1.5 um and HAFO 2.5 um
libraries.
- Jiri Gaisler
European Space Research and Technology Centre
[ Editor's Note: Jiri (and other ESNUG readers), if you have a script that's
handy please send it in when you write me. That way I don't have to chase
*you* later when people chase *me* to get *your* script! ;^) -John ]
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