( ESNUG 205 Item 3 ) ---------------------------------------------- [12/16/94]
Subject: (ESNUG 204 #6) "Seeking Best Verilog to FPGA Design Path"
>We're interested in putting together a Verilog -> FPGA development path. We
>own Design Compiler Expert, Xact, Neocad. We've identified three plausible
>paths, each with different costs and benefits and I'm interested in other's
>experiences with this problem, so we can focus on the approaches most likely
>to be successful.
From: markp@edassc.com (Mark Papamarcos)
My direct experience with using DC-Expert and FPGA Compiler on the same design
suggests that FPGA Compiler can do a substantially better job in some cases.
In particular, in a recent XC4013 design with a lot of register-intensive
datapaths and LFSR's, FPGA Compiler was able to cut out over 20% of the CLB's
simply by use of clock enables. DC-Expert did not perform this Xilinx
specific optimization. This also greatly enhanced performance by reducing
logic levels and getting logic into single CLBs which formerly couldn't fit.
The other FPGA Compiler feature which helped us a lot was the feeding forward
of timing constraints. While the timing models in FPGA Compiler are still
not great, this did save considerable effort in the normally ponderous task
of constraining Xilinx's place & route, even when the initial implementation
of this feature in 3.1a was very buggy.
- Mark Papamarcos
EDA Associates
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From: taub@corp.cirrus.com (Ed Taub)
John,
We did a HW emulator using a single Xilinx + Synopsys FPGA compiler to XACT.
(I am giving a talk on it at Design Supercon 95 on ASIC verification.)
The only problems we found were a failure of FPGA compiler to produce a latch
when we gave it an ...else latcha=latcha clause. We had to delete the "else"
to force a latch. Design Compiler bought the original syntax and did
synthesize correctly.
Also, there is a bit of magic to get bidi external I/O pins to work correctly.
You also need to know how to limit use of special clock driver I/O pins in
Xilinx. The XACT software foolishy assigns too many signals and exceeds the
number of pins unless you designate which pins are actually the system clock.
I heartily recommend this path if you are already using Verilog/Synopsys. We
got excellent results and barely had to read the manuals. It has saved many
many tapeouts.
- Ed Taub
Cirrus Logic
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