( ESNUG 203 Item 2 ) ---------------------------------------------- [12/2/94]
Subject: (ESNUG 202 #5) Synthesizable Yet Unsimulateble Verilog Code (!?)
>In a project involving both Verilog and VHDL we stumbled upon Verilog
>code which is synthesizable (Synopsys 3.0c) but that cannot be simulated
>(Veriwell). When trying to do "non-constant valued part-selects", like:
>
> for (i=1; i <= 7; i=i+1) begin
> a[i-1] = {b[7-i:0], zeros[i-1:0]};
> end
>
>the synthesis tool gives you the circuit you would expect, but the simulator
>doesn't accept it! I remember from my pre-VHDL life (3 years ago) that this
>is indeed a Verilog restriction: part-selects should be "constant-valued".
From: prasad@lsil.com (Prasad Paranjpe)
John,
I'd like to verify this problem. (I have been trying to build muxes the way
I do in VHDL as parameterized designs. This way I build ONE mux template and
elaborate any mux I want by changing the parameters. This is not as nice as
using an array of arrays in the port declaration but then again this _is_
Verilog. :^) )
From the Cadence Verilog-XL reference (p 4-17) Section 4.2.1 - Net & Register
Bit Addressing - paragraph 5:
vect[ms_expr:ls_expr]
Both expressions must be constant expressions. The first expression
must address a more significant bit than the second expression.
Compiler errors will result if either of these rules is broken.
I, too, could synthesize this type of code but when I tried to run the source
in Verilog-XL 2.0.5, I got:
Error! Non-constant part-select index [Verilog-NCPSI]
"muxMto1.v", 25: D[ti:bi]
- Prasad Paranjpe
LSI Logic
--- --- --- ---
John,
We sent an enhancement request to Cadence on this matter in 12/92 (PCR 82530).
As of 10/94, it has not yet been changed, to the best of our knowledge.
- Shalom Bresticker
Motorola Semiconductor Israel, Ltd.
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