( ESNUG 202 Item 1 ) ---------------------------------------------- [11/18/94]
From: ggrover@procy.gi.com (glen grover)
Subject: A Smattering Of Workarounds Useful In Converting To 3.1
John,
Here's a list of the myriad workarounds that I have had the pleasure :^) of
using while trying to convert to version 3.1:
1) compile_implementation_selection = false
Turns off re-eval of synthetic library implementation selections during the
compile.
2) compile_use_low_timing_effort = true
Causes optimization to use estimated output transitions rather than precise
calculations based on input slew rate. This could cause small violations
in edge rate. (This will only affect compile time if the target library
specifies this relation between input slew and output transition time.)
3) new_seqmap_effort = 1
Lowers the effort of the new sequential mapping algorithm.
4) hdlin_force_use_ffgen = true (or hdlin_seq_device_v30_mode = true)
improved_seqmap = 0
disable_sequential_degeneration = 0
These turn off new sequential mapping algorithms completely (!?!).
Compile times do increase, but not to level of version 3.0c.
5) hlo_minimize_tree_delay = false
Disables algorithm which tries to rearrange associative and commutative
operations in order to shorten critical paths. (This was used to eliminate
a fatal crash for a particular module).
6) hdlin_ff_always_sync_set_reset = true
I used this switch on modules which had no asynchronous sets or resets.
This tells synopsys to treat any =0 or =1 assignments within clocked blocks
as synchronous resets or sets. (I think version 3.0c did this by default).
Anyways, this improved compile time in modules that had significant numbers
of sequential logic.
Regarding (ESNUG 200 #6): Synopsys version 3.1a/b dramatically increased
compile times for the CMOS2 delay model and the suggested workaround of:
set_attribute find(library, your_library) delay_model "generic_cmos"
This workaround does not revert to 3.0 mapping and thus retains the advantages
gained by the new sequential algorithms. Not every library uses the CMOS2
delay models, so this workaround may not help in your case... check your
library.
- Glen Grover
General Instrument, San Diego
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