( ESNUG 201 Item 3 ) ---------------------------------------------- [11/10/94]
Subject: (ESNUG 200 #6) Concerns About SolvIt Solution To CMOS2 Long Runtimes
>I am seeing excessively long compile times with ver. 3.1b for sequential
>logic. The suggested workaround (SolvIt QA-008611):
>
>> Workaround:
>>
>> read -f vhdl design.vhd
>> read h4c.db
>> set_attribute find(library, h4c) delay_model "generic_cmos" ......
From: [ A Synopsys Apps Engineer ]
Hi John -- the SolvIt article, QA-008611, does not exist. (We've had people
polling SolvIt trying to download it. The text he quoted is actually
from article QA-009985.) The workaround explained in article QA-009985 only
works with the CMOS2 delay model.
Concerning the user's question of:
>This is a method of reverting back to 3.0 compatability and it makes me
>wonder what the new release brings to the party. The following variables
>(that weren't mentioned in this SolvIt write-up) reduce the compile time,
>but I wonder if there's some unseen penalty I'm paying using them...
I'd like to point out SolvIt article QA-010021. (Which can also be found in
the v3.1b release notes.)
"In v3.1b and v3.2a, improvements have been made to the compilation
time with non-linear delay model libraries and CMOS2 libraries,
respectively. If you feel your runtimes are still too long, the
following workarounds will still be effective.
WORKAROUNDS:
FOR NON-LINEAR DELAY MODEL:
1. Compile with compile_use_low_timing_effort = "true". This switch
only affects compile, your timing reports will be produced using
exact timing. During compile, approximate delays will be used for
input transitions.
2. Set the variable new_seqmap_effort = 1 before compilation. This
runs the v3.1a sequential mapping algorithms at a lower effort level.
3. Before reading in or analyzing the VHDL, set the variable
hdlin_seq_device_v30_mode = true. Then before compilation, set
improved_seqmap = 0 and disable_sequential_degeneration = 0. This
will completely turn off the v3.1a sequential mapping algorithms and
revert back to v3.0x method of sequential mapping.
Try the workarounds in the following order: #1 alone, #1 and #2, #1 and #3.
FOR CMOS2 DELAY MODEL:
1. Set the variable new_seqmap_effort = 1 before compilation. This
runs the v3.1a sequential mapping algorithms at a lower effort level.
2. Before reading in or analyzing the VHDL, set the variable
hdlin_seq_device_v30_mode = true. Then before compilation, set
improved_seqmap = 0 and disable_sequential_degeneration = 0. This
will completely turn off the v3.1a sequential mapping algorithms and
revert back to v3.0x method of sequential mapping."
NOTE: hdlin_seq_device_v30_mode is a v3.1b variable.
- [ A Synopsys Apps Engineer ]
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