( ESNUG 197 Item 3 ) ---------------------------------------------- [10/6/94]
Subject: (ESNUG 195 #0 196 #2 ) "Synopsys Announcing DesignPower"
>I wouldn't start counting your sheep just yet. Many Verilog-XL users have
>written "toggle count" PLI programs to estimate the switching frequency of
>their gates. They multiply the frequency times some AC power factor to get
>the total power consumption. This was done even before Synopsys was around.
From: mark_indovina@pts.mot.com (Mark Indovina)
Hi John,
I must concurr with the above user; a toggle test PLI function source code
is shipped with the Cadence Verilog distribution. For example, take a peek
at the May 1-4, 1994 Proceeding of the IEEE 1994 Custom Integrated Circuits
Conference. Of particular interest is paper 11.5 "Power Analysis for
Semi-Custom Design", written by some dudes at Motorola's Advanced Design
Technology Center in Tempe, AZ. This paper describes some internally
developed tools called "Entice" and "Aspen". Entice is a circuit
characterization tool; Aspen is a power analysis system (which is primarily
C/Verilog PLI) which reads the Entice database for power vectors when a cell
port transition is detected in the simulator. No GUI but what the hey ...
look for it at Babagges!
- Mark A. Indovina
Motorola
---- ---- ---- ----
From: stevem@siecomp.com (Steve McChrystal)
John,
It is not clear from your comments on DesignPower what they actually are
doing, but the idea of calculating dynamic power during VHDL (or Verilog)
simulation is due.
With an event driven simulator, why can't a quantum of power be tallied
with each transition of a CMOS gate? The situation is similar to
back-annotated timing simulation, where an intrinsic delay is added to
a loading delay calculated from estimated or layout interconnect data.
The gate model could treat power the same way, with a characterized
internal power and a loading derived interconnect power.
Of course it would suffer the same problem as detailed timing analysis
- you'd have to run real simulations, but this is far better than the
various guess methods used currently. Any ideas out there ?
- Steve McChrystal
Siemens ICD, Cupertino, CA
---- ---- ---- ----
>If you have to use simulation vectors to estimate power, then DesignPower is
>nothing like a static timing analyzer. Worse yet, if you expect to run
>simulations in the middle of a synthesis job to see how well you are meeting
>your power budget, you better be prepared to wait a while.
From: kgomes@Synopsys.COM (Kelly Gomes) [ plus Synopsys R & D and CAE ]
DesignPower is a new gate-level power analysis tool that enables RTL and
gate level design tradeoffs and library tradeoffs for power. The really
new technology here is the probabilistic approach and the robust power
model that enables the designers to do RTL-level, gate-level and library
experimentation. It *is* analogous to static timing analysis in its usage
model.
This tool will help designers in estimating the power consumption early
in the design cycle & guide them to ultimately meet their power constraint
specification. This has been accomplished by two fundamental approaches:
The first approach is based on probabilistic estimation technique. This
approach gives the designer a fast power estimation early in the design
cycle without having to simulate the design.
This probability based estimation technique uses switching activity
information provided by the designer only for the "primary inputs".
DesignPower uses this switching activity to compute the toggle rates
& static probability for all the internal nodes (also referred to as
switching activity). Using switching activity of internal nodes in
the design in conjunction with the voltage & capacitance values from
the technology library, DesignPower calculates the final power
estimation of the design.
In the second approach, DesignPower uses switching activity based on
the information generated by VHDL or Verilog gate level simulator. The
simulator provides switching activity for all the internal nodes and
this is used to calculate the power estimate of the design.
An important fact to note here is that DesignPower calculates Static
as well as Dynamic power dissipation in the design. Both the components
of the dynamic power dissipation; Switching power dissipation and
Internal power dissipation; are taken into consideration while
computing the total power dissipation. Thus we can assure the user
base that DesignPower does far more complex calculations using
different complex algorithms than simply multiply the frequency with
AC power factor to get the total power consumption.
- Kelly Gomes, Synopsys Marketing
[ Synopsys R & D ]
[ Synopsys Corporate Applications Engineering ]
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