( ESNUG 196 Item 2 ) ---------------------------------------------- [9/29/94]
Subject: (ESNUG 195 #0) "Synopsys Announcing DesignPower"
> Editor's Note: Synopsys just announced that it's going to sell a tool
> called DesignPower that's to be used to do probabalistic power analysis on
> switching CMOS type designs. (It's sort of like a "power" equivalent of
> a static timing analyzer -- you throw vectors at the design in this tool
> and it looks at what gates switched and what didn't from a power point of
> view.) I'm very excited about this -- not the product, but what it
> signifies -- Synopsys is going to start looking at power as a user
> controllable constraint to synthesis! Cool!
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From: david@nextwave.com (David Rich)
John,
I wouldn't start counting your sheep just yet. Many Verilog-XL users have
written "toggle count" PLI programs to estimate the switching frequency of
their gates. They multiply the frequency times some AC power factor to get
the total power consumption. This was being done even before Synopsys was
around.
If you have to use simulation vectors to estimate power, then DesignPower is
nothing like a static timing analyzer. Worse yet, if you expect to run
simulations in the middle of a synthesis job to see how well you are meeting
your power budget, you better be prepared to wait a while.
- Dave Rich
ex-Cadence, now at Nextwave Design
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