( ESNUG 191 Item 2 ) ---------------------------------------------- [7/28/94]
From: Brian Arnold <bka@hpesbka.fc.hp.com>
Subject: DC 3.1a Poorly Choosing Gates
John,
One especially obnoxious bug we have been running into with 3.1a is the
frequency which Synopsys is selecting suboptimal cells. What is meant by
this is Synopsys is choosing a cell with seven inputs (for example) when a
more appropriate choice would be a cell with four inputs. The remainder of
the inputs that are not used are then tied off to either logic0 or logic1
depending on the function. These cells that are being selected are specialty
cells with a complex function, not just AND or OR. The synthesized logic is
correct, but the area and delay are both greater.
One method I tried to erradicate this behavior is to insert two additional
cells into the library which represent the functions "0" and "1". When these
cells are included in the library they will be used instead of Synopsys'
internal cells, "logic0" and "logic1". I have attached to each of these cells
a tremendous amount of area so the cost of selecting them is great and
Synopsys would decide to not use a suboptimal cell where it would have to
utilize these large area cells to complete the function. This approach has
seen limited success but still insists on using suboptimal cells and tieing
the unused inputs off.
Has anybody else been dealing with this, and if so what is your solution?
- Brian Arnold
Hewlet-Packard
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