!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / INDUSTRY GADFLY: "Reading EDA Tea Leaves"
_] [_
by John Cooley, EE Times Columnist
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
If you want to know how the five way physical synthesis horse race is going,
you've got to track what the engineers who actually use such tools are
saying and, more importantly, the bugs they find. (You can find such talk
in newsgroups, on ESNUG, or wherever engineers hang out.) Everything else
is fluff to woo Wall Street and the more gullible EDA buyers. Engineers
who actually use a tool will have some praise and lots of gripes. It's
human nature. No software is bug free. When you're seeing lots of public
bug talk about a tool, you truely know that it's being widely used. When
you see only public happiness and sunshine about a tool; be aware that
you're the one being used.
Having said this, here's the early February status of the RTL-to-GDS-II
race. With the exception of Synopsys and Monterey, most of the EDA vendors
(Cadence, Avanti, and Magma) seem stuck in taxi cab mode with their physical
synthesis tools. Taxi cab mode is where the EDA vendor provides both their
software and their own engineers to drive the software at the customer site.
It means their software is too unstable for real customer use. Currently,
most of the 70 Big Money EDA Customers are "buying" only evaluation copies
and holding private taxi cab races -- which is why I laughed when newbie
Cadence CEO Ray Bingham bragged about PKS having 11 new "customers" in his
Jan. 25 press release. Ray's hotel finance background, with his lack of any
engineering experience, is clearly showing here.
The big breakthough happened 3 months ago when, a real chip designer, Bob
Prevett of NVidia wrote a detailed technical review in ESNUG 335 of PhysOpt
(now called Physical Compiler) from Synopsys. A week later, Matrox and
NVidia both announced they had done chip tapeouts with Physical Compiler.
Then another real chip designer, Jon Stahl of Avici, wrote a detailed
technical review of Synopsys Chip Architect in ESNUG 338. This means that
Synopsys is clearly moving out of taxi cab mode.
Cadence PKS was believed to be struggling with 3 conflicting timing engines
between PKS, Qplace, and Pearl. Then, last week in ESNUG 342, Jay McDougal
of Agilent reported only a 0-3 percent timing error between PKS, Qplace,
Pearl, and even PrimeTime. (Jay's short PKS comment last week is the first
known actual customer usage statement about PKS.)
Avanti and a very noisey Magma are playing up vague customer endorsements
in the press, but nothing verifiable of course. Monterey is just a town in
California. These are still taxi cab companies. So, with two customer
tapeouts versus a first customer mention, it appears that Synopsys is about
6 months ahead of Cadence in the physical synthesis domain. Now it's time
to watch the bug talk to see if they stay ahead or fall behind Cadence.
-----
John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a
contract ASIC designer, and loves hearing from engineers at
"jcooley@world.std.com" or (508) 429-4357.
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