| A little reminiscing … | |
| Introduction to NVIDIA | |
| Our Track Record | |
| Our Development Philosophy | |
| General Methodology Overview | |
| Typical Project Timeline | |
| Level of Investment | |
| When Harry met Sally … | |
| What keeps me up at night | |
| Where things are going |
| ~850 employees – publicly traded NVDA | |
| Recognized leader in 3D technology | |
| Broad product family | |
| 20% overall gfx market share and rapidly growing (48% standalone desktop) | |
| Named “100 Most Influential Technology Company” by Ziff Davis | |
| Expanding market - X-Box (consumer), Apple, mobile |
| Design for Correctness, and Time-To-Money | ||
| Goal of <= 1.5 spins to production | ||
| < 100 days 1st tapeout to production | ||
| Institutionalize best practices and exploit leverage | ||
| Constant and ongoing re-evaluation of “what” & “how” | ||
| Intellectual honesty, self-criticism | ||
| Everybody does everything | ||
| No product has to be perfect. | ||
| For if not this one then the next … | ||
| Verilog, full synthesis, static timing, simulation/emulation/formal | ||
| 1,2,4,8 | ||
| 1 conception, 2 implementations, 4 representations, 8 ways to verify | ||
| COT flow | ||
| 3rd party std. cells/RAMs, custom RAMs/PLL/DAC/IO | ||
| Historical two designs per technology (~ 1 process/year) | ||
| Priorities : schedule, performance/area | ||
| Multiple, overlapped design teams (3 teams, 2 seasons) | ||
| Constantly evolving methodology, partner with vendors | ||
| Typical 1.5 year schedule would have: | ||
| 1-2 months specification | ||
| 2-4 months of implementation | ||
| 3-9 months of verification | ||
| 1-2 months of physical design | ||
| ~$85M of CAD tools installed and online | ||
| over $80M acquired in the last 2-3 years ! | ||
| $15M - $20M Emulation installation | ||
| Engineering Compute resources | ||
| Desktops: 200 Sun/2150 PCs | ||
| Servers: 278 Sparc/Solaris, 634 x86/Linux, 496 Gbytes Ram | ||
| 14 Tera bytes of storage | ||
| Digital | ||
| EMACS and VI !! | ||
| RTL - Verilog | ||
| Simulators - Synopsys VCS, Cadence XL & NC, InnoLogic ESP-XV | ||
| Emulator - IKOS VLE | ||
| Synthesis - Synopsys Design Expert, Synopsys Module Compiler, Synopsys Physical Compiler | ||
| Test – Synopsys Sunrise, Synopsys TetraMax | ||
| Timing - Synopsys PrimeTime using SDF/DSPF or custom wireloads, Mentor Tau | ||
| Debug – Synopsys Virsim, Avant! Verilint, RealIntent Verex | ||
| Code Coverage - Synopsys Covermeter | ||
| test bench - in-house PLI-based and file-based environments | ||
| Formal Equivalency Checking - Synopsys Formality | ||
| Formal Model Checking - Averant Solidify | ||
| RAMS - in-house, compiled (Artisan) , custom | ||
| Libraries - 3rd party (Artisan) | ||
| version control - Perforce | ||
| machine (queue) management - Platform LSF | ||
| Mixed Signal | ||
| Layout editor - Cadence Virtuoso | ||
| simulators – Nassda HSIM, Avant! Hspice, Innologic ESP-CV | ||
| Substrate Design | ||
| Cadence APD | ||
| Layout | ||
| Avant! Apollo II P&R | ||
| Avant! Hercules II LVS/DRC | ||
| Avant! Star-RC 3D extractor | ||
| Synopsys Physical Compiler | ||
| Avant! Mars Rail | ||
| Power | ||
| Synopsys PowerCompiler | ||
| NVIDIA meets 3DFX who met GigaPixel | ||
| Similarities abound ! | ||
| The downsides (??) of near perfect retention | ||
| Try explaining everything you do ! … and why ! | ||
| The influence of your business model on your design methodology | ||
| Damn, I wish I thought of that … | ||
| Always worried that we’re lucky and not good … | |
| We have gotten good enough at the majority of things that the problems that we have left once we hit silicon are really tough !! | |
| We are becoming increasingly biased toward simple/predictable versus optimal | |
| Absolutely still true – if you don’t test or check it, it doesn’t work ! | |
| Our biggest problem is “getting it right” | |
| Convergence of methods to facilitate verification | ||
| Formal and Simulation based methods will work cooperatively | ||
| Logical and physical design will co-develop versus today’s more serial process | ||
| Both physically-aware synthesis and optimization-capable layout tools will coexist | ||
| All tools will need to embrace hierarchy to avoid unmanageable dB size | ||
| Mass acceptance of higher-level language HDLs will be preceeded by availability of high QOR behavioral compilers | ||
| LINUX based computing platforms will dominate EDA | ||