cycle: 0
cycle: 1
dmaConfig starting
cycle: 2
cycle: 3
cycle: 4
cycle: 5
cycle: 6
cycle: 7
cycle: 8
cycle: 9
cycle: 10
cycle: 11
cycle: 12
cycle: 13
cycle: 14
cycle: 15
cycle: 16
cycle: 17
cycle: 18
cycle: 19
cycle: 20
cycle: 21
cycle: 22
cycle: 23
cycle: 24
cycle: 25
cycle: 26
cycle: 27
DMAConfig done
cycle: 28
Starting the DMA controller channel 0
cycle: 29
cycle: 30
cycle: 31
cycle: 32
Target memA: Socket_Req{RD, 000, 00001000, 00000000}}
cycle: 33
Target memA: Socket_Req{RD, 000, 00001001, 00000000}}
cycle: 34
Target memA: Socket_Req{RD, 000, 00001002, 00000000}}
cycle: 35
cycle: 36
Target memA: Socket_Req{WR, 001, 00005000, 00001000}}
cycle: 37
cycle: 38
Target memA: Socket_Req{RD, 000, 00001003, 00000000}}
cycle: 39
Target memA: Socket_Req{WR, 001, 00005001, 00001001}}
cycle: 40
Target memA: Socket_Req{WR, 001, 00005002, 00001002}}
cycle: 41
Target memA: Socket_Req{RD, 000, 00001004, 00000000}}
cycle: 42
Target memA: Socket_Req{WR, 001, 00005003, 00001003}}
cycle: 43
Target memA: Socket_Req{RD, 000, 00001005, 00000000}}
cycle: 44
Target memA: Socket_Req{RD, 000, 00001006, 00000000}}
cycle: 45
Target memA: Socket_Req{WR, 001, 00005004, 00001004}}
cycle: 46
cycle: 47
Target memA: Socket_Req{RD, 000, 00001007, 00000000}}
cycle: 48
Target memA: Socket_Req{WR, 001, 00005005, 00001005}}
cycle: 49
Target memA: Socket_Req{WR, 001, 00005006, 00001006}}
cycle: 50
Target memA: Socket_Req{RD, 000, 00001008, 00000000}}
cycle: 51
Target memA: Socket_Req{WR, 001, 00005007, 00001007}}
cycle: 52
Target memA: Socket_Req{RD, 000, 00001009, 00000000}}
cycle: 53
Target memA: Socket_Req{RD, 000, 0000100a, 00000000}}
cycle: 54
Target memA: Socket_Req{WR, 001, 00005008, 00001008}}
cycle: 55
cycle: 56
Target memA: Socket_Req{RD, 000, 0000100b, 00000000}}
cycle: 57
Target memA: Socket_Req{WR, 001, 00005009, 00001009}}
cycle: 58
Target memA: Socket_Req{WR, 001, 0000500a, 0000100a}}
cycle: 59
Target memA: Socket_Req{RD, 000, 0000100c, 00000000}}
cycle: 60
Target memA: Socket_Req{WR, 001, 0000500b, 0000100b}}
cycle: 61
Target memA: Socket_Req{RD, 000, 0000100d, 00000000}}
cycle: 62
Target memA: Socket_Req{RD, 000, 0000100e, 00000000}}
cycle: 63
Target memA: Socket_Req{WR, 001, 0000500c, 0000100c}}
cycle: 64
cycle: 65
Target memA: Socket_Req{RD, 000, 0000100f, 00000000}}
cycle: 66
Target memA: Socket_Req{WR, 001, 0000500d, 0000100d}}
cycle: 67
Target memA: Socket_Req{WR, 001, 0000500e, 0000100e}}
cycle: 68
Target memA: Socket_Req{RD, 000, 00001010, 00000000}}
cycle: 69
Target memA: Socket_Req{WR, 001, 0000500f, 0000100f}}
cycle: 70
Target memA: Socket_Req{RD, 000, 00001011, 00000000}}
cycle: 71
Target memA: Socket_Req{RD, 000, 00001012, 00000000}}
cycle: 72
Target memA: Socket_Req{WR, 001, 00005010, 00001010}}
cycle: 73
cycle: 74
Target memA: Socket_Req{RD, 000, 00001013, 00000000}}
cycle: 75
Target memA: Socket_Req{WR, 001, 00005011, 00001011}}
cycle: 76
Target memA: Socket_Req{WR, 001, 00005012, 00001012}}
cycle: 77
cycle: 78
Target memA: Socket_Req{WR, 001, 00005013, 00001013}}
cycle: 79
cycle: 80
cycle: 81
cycle: 82
Channel 0 is complete.
cycle: 83
Finished  run of channel 0, starting channel 1
cycle: 84
cycle: 85
cycle: 86
cycle: 87
Target memA: Socket_Req{RD, 002, 00002000, 00000000}}
cycle: 88
Target memA: Socket_Req{RD, 002, 00002001, 00000000}}
cycle: 89
Target memA: Socket_Req{RD, 002, 00002002, 00000000}}
cycle: 90
cycle: 91
Target memA: Socket_Req{WR, 003, 00007000, 00002000}}
cycle: 92
cycle: 93
Target memA: Socket_Req{RD, 002, 00002003, 00000000}}
cycle: 94
Target memA: Socket_Req{WR, 003, 00007001, 00002001}}
cycle: 95
Target memA: Socket_Req{WR, 003, 00007002, 00002002}}
cycle: 96
Target memA: Socket_Req{RD, 002, 00002004, 00000000}}
cycle: 97
Target memA: Socket_Req{WR, 003, 00007003, 00002003}}
cycle: 98
Target memA: Socket_Req{RD, 002, 00002005, 00000000}}
cycle: 99
Target memA: Socket_Req{RD, 002, 00002006, 00000000}}
cycle: 100
Target memA: Socket_Req{WR, 003, 00007004, 00002004}}
cycle: 101
cycle: 102
Target memA: Socket_Req{RD, 002, 00002007, 00000000}}
cycle: 103
Target memA: Socket_Req{WR, 003, 00007005, 00002005}}
cycle: 104
Target memA: Socket_Req{WR, 003, 00007006, 00002006}}
cycle: 105
Target memA: Socket_Req{RD, 002, 00002008, 00000000}}
cycle: 106
Target memA: Socket_Req{WR, 003, 00007007, 00002007}}
cycle: 107
Target memA: Socket_Req{RD, 002, 00002009, 00000000}}
cycle: 108
Target memA: Socket_Req{RD, 002, 0000200a, 00000000}}
cycle: 109
Target memA: Socket_Req{WR, 003, 00007008, 00002008}}
cycle: 110
cycle: 111
Target memA: Socket_Req{RD, 002, 0000200b, 00000000}}
cycle: 112
Target memA: Socket_Req{WR, 003, 00007009, 00002009}}
cycle: 113
Target memA: Socket_Req{WR, 003, 0000700a, 0000200a}}
cycle: 114
Target memA: Socket_Req{RD, 002, 0000200c, 00000000}}
cycle: 115
Target memA: Socket_Req{WR, 003, 0000700b, 0000200b}}
cycle: 116
Target memA: Socket_Req{RD, 002, 0000200d, 00000000}}
cycle: 117
Target memA: Socket_Req{RD, 002, 0000200e, 00000000}}
cycle: 118
Target memA: Socket_Req{WR, 003, 0000700c, 0000200c}}
cycle: 119
cycle: 120
Target memA: Socket_Req{RD, 002, 0000200f, 00000000}}
cycle: 121
Target memA: Socket_Req{WR, 003, 0000700d, 0000200d}}
cycle: 122
Target memA: Socket_Req{WR, 003, 0000700e, 0000200e}}
cycle: 123
Target memA: Socket_Req{RD, 002, 00002010, 00000000}}
cycle: 124
Target memA: Socket_Req{WR, 003, 0000700f, 0000200f}}
cycle: 125
Target memA: Socket_Req{RD, 002, 00002011, 00000000}}
cycle: 126
Target memA: Socket_Req{RD, 002, 00002012, 00000000}}
cycle: 127
Target memA: Socket_Req{WR, 003, 00007010, 00002010}}
cycle: 128
cycle: 129
Target memA: Socket_Req{RD, 002, 00002013, 00000000}}
cycle: 130
Target memA: Socket_Req{WR, 003, 00007011, 00002011}}
cycle: 131
Target memA: Socket_Req{WR, 003, 00007012, 00002012}}
cycle: 132
cycle: 133
Target memA: Socket_Req{WR, 003, 00007013, 00002013}}
cycle: 134
cycle: 135
cycle: 136
cycle: 137
Channel 1 is complete.
cycle: 138
Finished  run of channel 1, starting channel 2
cycle: 139
cycle: 140
cycle: 141
cycle: 142
Target memA: Socket_Req{RD, 004, 00003000, 00000000}}
cycle: 143
Target memA: Socket_Req{RD, 004, 00003001, 00000000}}
cycle: 144
Target memA: Socket_Req{RD, 004, 00003002, 00000000}}
cycle: 145
cycle: 146
Target memA: Socket_Req{WR, 005, 00004000, 00003000}}
cycle: 147
cycle: 148
Target memA: Socket_Req{RD, 004, 00003003, 00000000}}
cycle: 149
Target memA: Socket_Req{WR, 005, 00004001, 00003001}}
cycle: 150
Target memA: Socket_Req{WR, 005, 00004002, 00003002}}
cycle: 151
Target memA: Socket_Req{RD, 004, 00003004, 00000000}}
cycle: 152
Target memA: Socket_Req{WR, 005, 00004003, 00003003}}
cycle: 153
Target memA: Socket_Req{RD, 004, 00003005, 00000000}}
cycle: 154
Target memA: Socket_Req{RD, 004, 00003006, 00000000}}
cycle: 155
Target memA: Socket_Req{WR, 005, 00004004, 00003004}}
cycle: 156
cycle: 157
Target memA: Socket_Req{RD, 004, 00003007, 00000000}}
cycle: 158
Target memA: Socket_Req{WR, 005, 00004005, 00003005}}
cycle: 159
Target memA: Socket_Req{WR, 005, 00004006, 00003006}}
cycle: 160
Target memA: Socket_Req{RD, 004, 00003008, 00000000}}
cycle: 161
Target memA: Socket_Req{WR, 005, 00004007, 00003007}}
cycle: 162
Target memA: Socket_Req{RD, 004, 00003009, 00000000}}
cycle: 163
Target memA: Socket_Req{RD, 004, 0000300a, 00000000}}
cycle: 164
Target memA: Socket_Req{WR, 005, 00004008, 00003008}}
cycle: 165
cycle: 166
Target memA: Socket_Req{RD, 004, 0000300b, 00000000}}
cycle: 167
Target memA: Socket_Req{WR, 005, 00004009, 00003009}}
cycle: 168
Target memA: Socket_Req{WR, 005, 0000400a, 0000300a}}
cycle: 169
Target memA: Socket_Req{RD, 004, 0000300c, 00000000}}
cycle: 170
Target memA: Socket_Req{WR, 005, 0000400b, 0000300b}}
cycle: 171
Target memA: Socket_Req{RD, 004, 0000300d, 00000000}}
cycle: 172
Target memA: Socket_Req{RD, 004, 0000300e, 00000000}}
cycle: 173
Target memA: Socket_Req{WR, 005, 0000400c, 0000300c}}
cycle: 174
cycle: 175
Target memA: Socket_Req{RD, 004, 0000300f, 00000000}}
cycle: 176
Target memA: Socket_Req{WR, 005, 0000400d, 0000300d}}
cycle: 177
Target memA: Socket_Req{WR, 005, 0000400e, 0000300e}}
cycle: 178
Target memA: Socket_Req{RD, 004, 00003010, 00000000}}
cycle: 179
Target memA: Socket_Req{WR, 005, 0000400f, 0000300f}}
cycle: 180
Target memA: Socket_Req{RD, 004, 00003011, 00000000}}
cycle: 181
Target memA: Socket_Req{RD, 004, 00003012, 00000000}}
cycle: 182
Target memA: Socket_Req{WR, 005, 00004010, 00003010}}
cycle: 183
cycle: 184
Target memA: Socket_Req{RD, 004, 00003013, 00000000}}
cycle: 185
Target memA: Socket_Req{WR, 005, 00004011, 00003011}}
cycle: 186
Target memA: Socket_Req{WR, 005, 00004012, 00003012}}
cycle: 187
cycle: 188
Target memA: Socket_Req{WR, 005, 00004013, 00003013}}
cycle: 189
cycle: 190
cycle: 191
cycle: 192
Channel 2 is complete.
cycle: 193
Finished  run of channel 2, starting channel 3
cycle: 194
cycle: 195
cycle: 196
cycle: 197
Target memA: Socket_Req{RD, 006, 00004000, 00000000}}
cycle: 198
Target memA: Socket_Req{RD, 006, 00004001, 00000000}}
cycle: 199
Target memA: Socket_Req{RD, 006, 00004002, 00000000}}
cycle: 200
cycle: 201
Target memA: Socket_Req{WR, 007, 00006000, 00004000}}
cycle: 202
cycle: 203
Target memA: Socket_Req{RD, 006, 00004003, 00000000}}
cycle: 204
Target memA: Socket_Req{WR, 007, 00006001, 00004001}}
cycle: 205
Target memA: Socket_Req{WR, 007, 00006002, 00004002}}
cycle: 206
Target memA: Socket_Req{RD, 006, 00004004, 00000000}}
cycle: 207
Target memA: Socket_Req{WR, 007, 00006003, 00004003}}
cycle: 208
Target memA: Socket_Req{RD, 006, 00004005, 00000000}}
cycle: 209
Target memA: Socket_Req{RD, 006, 00004006, 00000000}}
cycle: 210
Target memA: Socket_Req{WR, 007, 00006004, 00004004}}
cycle: 211
cycle: 212
Target memA: Socket_Req{RD, 006, 00004007, 00000000}}
cycle: 213
Target memA: Socket_Req{WR, 007, 00006005, 00004005}}
cycle: 214
Target memA: Socket_Req{WR, 007, 00006006, 00004006}}
cycle: 215
Target memA: Socket_Req{RD, 006, 00004008, 00000000}}
cycle: 216
Target memA: Socket_Req{WR, 007, 00006007, 00004007}}
cycle: 217
Target memA: Socket_Req{RD, 006, 00004009, 00000000}}
cycle: 218
Target memA: Socket_Req{RD, 006, 0000400a, 00000000}}
cycle: 219
Target memA: Socket_Req{WR, 007, 00006008, 00004008}}
cycle: 220
cycle: 221
Target memA: Socket_Req{RD, 006, 0000400b, 00000000}}
cycle: 222
Target memA: Socket_Req{WR, 007, 00006009, 00004009}}
cycle: 223
Target memA: Socket_Req{WR, 007, 0000600a, 0000400a}}
cycle: 224
Target memA: Socket_Req{RD, 006, 0000400c, 00000000}}
cycle: 225
Target memA: Socket_Req{WR, 007, 0000600b, 0000400b}}
cycle: 226
Target memA: Socket_Req{RD, 006, 0000400d, 00000000}}
cycle: 227
Target memA: Socket_Req{RD, 006, 0000400e, 00000000}}
cycle: 228
Target memA: Socket_Req{WR, 007, 0000600c, 0000400c}}
cycle: 229
cycle: 230
Target memA: Socket_Req{RD, 006, 0000400f, 00000000}}
cycle: 231
Target memA: Socket_Req{WR, 007, 0000600d, 0000400d}}
cycle: 232
Target memA: Socket_Req{WR, 007, 0000600e, 0000400e}}
cycle: 233
Target memA: Socket_Req{RD, 006, 00004010, 00000000}}
cycle: 234
Target memA: Socket_Req{WR, 007, 0000600f, 0000400f}}
cycle: 235
Target memA: Socket_Req{RD, 006, 00004011, 00000000}}
cycle: 236
Target memA: Socket_Req{RD, 006, 00004012, 00000000}}
cycle: 237
Target memA: Socket_Req{WR, 007, 00006010, 00004010}}
cycle: 238
cycle: 239
Target memA: Socket_Req{RD, 006, 00004013, 00000000}}
cycle: 240
Target memA: Socket_Req{WR, 007, 00006011, 00004011}}
cycle: 241
Target memA: Socket_Req{WR, 007, 00006012, 00004012}}
cycle: 242
cycle: 243
Target memA: Socket_Req{WR, 007, 00006013, 00004013}}
cycle: 244
cycle: 245
cycle: 246
cycle: 247
Channel 3 is complete.
cycle: 248
Finished  run of channel 3, starting all channels
cycle: 249
cycle: 250
All channels started
cycle: 251
cycle: 252
Target memA: Socket_Req{RD, 000, 00001014, 00000000}}
cycle: 253
Target memA: Socket_Req{RD, 000, 00001015, 00000000}}
cycle: 254
Target memA: Socket_Req{RD, 000, 00001016, 00000000}}
cycle: 255
cycle: 256
Target memA: Socket_Req{RD, 002, 00002014, 00000000}}
cycle: 257
cycle: 258
Target memA: Socket_Req{WR, 001, 00005014, 00001014}}
cycle: 259
Target memA: Socket_Req{WR, 001, 00005015, 00001015}}
cycle: 260
Target memA: Socket_Req{WR, 001, 00005016, 00001016}}
cycle: 261
Target memA: Socket_Req{RD, 000, 00001017, 00000000}}
cycle: 262
Target memA: Socket_Req{RD, 000, 00001018, 00000000}}
cycle: 263
Target memA: Socket_Req{RD, 000, 00001019, 00000000}}
cycle: 264
cycle: 265
Target memA: Socket_Req{WR, 003, 00007014, 00002014}}
cycle: 266
cycle: 267
Target memA: Socket_Req{WR, 001, 00005017, 00001017}}
cycle: 268
Target memA: Socket_Req{WR, 001, 00005018, 00001018}}
cycle: 269
Target memA: Socket_Req{WR, 001, 00005019, 00001019}}
cycle: 270
Target memA: Socket_Req{RD, 000, 0000101a, 00000000}}
cycle: 271
Target memA: Socket_Req{RD, 000, 0000101b, 00000000}}
cycle: 272
Target memA: Socket_Req{RD, 000, 0000101c, 00000000}}
cycle: 273
cycle: 274
Target memA: Socket_Req{RD, 002, 00002015, 00000000}}
cycle: 275
cycle: 276
Target memA: Socket_Req{WR, 001, 0000501a, 0000101a}}
cycle: 277
Target memA: Socket_Req{WR, 001, 0000501b, 0000101b}}
cycle: 278
Target memA: Socket_Req{WR, 001, 0000501c, 0000101c}}
cycle: 279
Target memA: Socket_Req{RD, 000, 0000101d, 00000000}}
cycle: 280
Target memA: Socket_Req{RD, 000, 0000101e, 00000000}}
cycle: 281
Target memA: Socket_Req{RD, 000, 0000101f, 00000000}}
cycle: 282
cycle: 283
Target memA: Socket_Req{WR, 003, 00007015, 00002015}}
cycle: 284
cycle: 285
Target memA: Socket_Req{WR, 001, 0000501d, 0000101d}}
cycle: 286
Target memA: Socket_Req{WR, 001, 0000501e, 0000101e}}
cycle: 287
Target memA: Socket_Req{WR, 001, 0000501f, 0000101f}}
cycle: 288
Target memA: Socket_Req{RD, 000, 00001020, 00000000}}
cycle: 289
Target memA: Socket_Req{RD, 000, 00001021, 00000000}}
cycle: 290
Target memA: Socket_Req{RD, 000, 00001022, 00000000}}
cycle: 291
cycle: 292
Target memA: Socket_Req{RD, 002, 00002016, 00000000}}
cycle: 293
cycle: 294
Target memA: Socket_Req{WR, 001, 00005020, 00001020}}
cycle: 295
Target memA: Socket_Req{WR, 001, 00005021, 00001021}}
cycle: 296
Target memA: Socket_Req{WR, 001, 00005022, 00001022}}
cycle: 297
Target memA: Socket_Req{RD, 000, 00001023, 00000000}}
cycle: 298
Target memA: Socket_Req{RD, 000, 00001024, 00000000}}
cycle: 299
Target memA: Socket_Req{RD, 000, 00001025, 00000000}}
cycle: 300
cycle: 301
Target memA: Socket_Req{WR, 003, 00007016, 00002016}}
cycle: 302
cycle: 303
Target memA: Socket_Req{WR, 001, 00005023, 00001023}}
cycle: 304
Target memA: Socket_Req{WR, 001, 00005024, 00001024}}
cycle: 305
Target memA: Socket_Req{WR, 001, 00005025, 00001025}}
cycle: 306
Target memA: Socket_Req{RD, 000, 00001026, 00000000}}
cycle: 307
Target memA: Socket_Req{RD, 000, 00001027, 00000000}}
cycle: 308
Target memA: Socket_Req{RD, 002, 00002017, 00000000}}
cycle: 309
cycle: 310
Target memA: Socket_Req{RD, 002, 00002018, 00000000}}
cycle: 311
Target memA: Socket_Req{WR, 001, 00005026, 00001026}}
cycle: 312
cycle: 313
Target memA: Socket_Req{WR, 001, 00005027, 00001027}}
cycle: 314
Target memA: Socket_Req{WR, 003, 00007017, 00002017}}
cycle: 315
Target memA: Socket_Req{WR, 003, 00007018, 00002018}}
cycle: 316
Target memA: Socket_Req{RD, 002, 00002019, 00000000}}
cycle: 317
Channel 0 is complete.
Target memA: Socket_Req{RD, 002, 0000201a, 00000000}}
cycle: 318
Target memA: Socket_Req{RD, 002, 0000201b, 00000000}}
cycle: 319
cycle: 320
Target memA: Socket_Req{RD, 004, 00003014, 00000000}}
cycle: 321
cycle: 322
Target memA: Socket_Req{WR, 003, 00007019, 00002019}}
cycle: 323
Target memA: Socket_Req{WR, 003, 0000701a, 0000201a}}
cycle: 324
Target memA: Socket_Req{WR, 003, 0000701b, 0000201b}}
cycle: 325
Target memA: Socket_Req{RD, 002, 0000201c, 00000000}}
cycle: 326
Target memA: Socket_Req{RD, 002, 0000201d, 00000000}}
cycle: 327
Target memA: Socket_Req{RD, 002, 0000201e, 00000000}}
cycle: 328
cycle: 329
Target memA: Socket_Req{WR, 005, 00004014, 00003014}}
cycle: 330
cycle: 331
Target memA: Socket_Req{WR, 003, 0000701c, 0000201c}}
cycle: 332
Target memA: Socket_Req{WR, 003, 0000701d, 0000201d}}
cycle: 333
Target memA: Socket_Req{WR, 003, 0000701e, 0000201e}}
cycle: 334
Target memA: Socket_Req{RD, 002, 0000201f, 00000000}}
cycle: 335
Target memA: Socket_Req{RD, 002, 00002020, 00000000}}
cycle: 336
Target memA: Socket_Req{RD, 002, 00002021, 00000000}}
cycle: 337
cycle: 338
Target memA: Socket_Req{RD, 004, 00003015, 00000000}}
cycle: 339
cycle: 340
Target memA: Socket_Req{WR, 003, 0000701f, 0000201f}}
cycle: 341
Target memA: Socket_Req{WR, 003, 00007020, 00002020}}
cycle: 342
Target memA: Socket_Req{WR, 003, 00007021, 00002021}}
cycle: 343
Target memA: Socket_Req{RD, 002, 00002022, 00000000}}
cycle: 344
Target memA: Socket_Req{RD, 002, 00002023, 00000000}}
cycle: 345
Target memA: Socket_Req{RD, 002, 00002024, 00000000}}
cycle: 346
cycle: 347
Target memA: Socket_Req{WR, 005, 00004015, 00003015}}
cycle: 348
cycle: 349
Target memA: Socket_Req{WR, 003, 00007022, 00002022}}
cycle: 350
Target memA: Socket_Req{WR, 003, 00007023, 00002023}}
cycle: 351
Target memA: Socket_Req{WR, 003, 00007024, 00002024}}
cycle: 352
Target memA: Socket_Req{RD, 002, 00002025, 00000000}}
cycle: 353
Target memA: Socket_Req{RD, 002, 00002026, 00000000}}
cycle: 354
Target memA: Socket_Req{RD, 002, 00002027, 00000000}}
cycle: 355
cycle: 356
Target memA: Socket_Req{RD, 004, 00003016, 00000000}}
cycle: 357
cycle: 358
Target memA: Socket_Req{WR, 003, 00007025, 00002025}}
cycle: 359
Target memA: Socket_Req{WR, 003, 00007026, 00002026}}
cycle: 360
Target memA: Socket_Req{WR, 003, 00007027, 00002027}}
cycle: 361
Target memA: Socket_Req{WR, 005, 00004016, 00003016}}
cycle: 362
Target memA: Socket_Req{RD, 004, 00003017, 00000000}}
cycle: 363
Target memA: Socket_Req{RD, 004, 00003018, 00000000}}
cycle: 364
Channel 1 is complete.
Target memA: Socket_Req{RD, 004, 00003019, 00000000}}
cycle: 365
cycle: 366
Target memA: Socket_Req{RD, 006, 00004014, 00000000}}
cycle: 367
cycle: 368
Target memA: Socket_Req{WR, 005, 00004017, 00003017}}
cycle: 369
Target memA: Socket_Req{WR, 005, 00004018, 00003018}}
cycle: 370
Target memA: Socket_Req{WR, 005, 00004019, 00003019}}
cycle: 371
Target memA: Socket_Req{RD, 004, 0000301a, 00000000}}
cycle: 372
Target memA: Socket_Req{RD, 004, 0000301b, 00000000}}
cycle: 373
Target memA: Socket_Req{RD, 004, 0000301c, 00000000}}
cycle: 374
cycle: 375
Target memA: Socket_Req{WR, 007, 00006014, 00004014}}
cycle: 376
cycle: 377
Target memA: Socket_Req{WR, 005, 0000401a, 0000301a}}
cycle: 378
Target memA: Socket_Req{WR, 005, 0000401b, 0000301b}}
cycle: 379
Target memA: Socket_Req{WR, 005, 0000401c, 0000301c}}
cycle: 380
Target memA: Socket_Req{RD, 004, 0000301d, 00000000}}
cycle: 381
Target memA: Socket_Req{RD, 004, 0000301e, 00000000}}
cycle: 382
Target memA: Socket_Req{RD, 004, 0000301f, 00000000}}
cycle: 383
cycle: 384
Target memA: Socket_Req{RD, 006, 00004015, 00000000}}
cycle: 385
cycle: 386
Target memA: Socket_Req{WR, 005, 0000401d, 0000301d}}
cycle: 387
Target memA: Socket_Req{WR, 005, 0000401e, 0000301e}}
cycle: 388
Target memA: Socket_Req{WR, 005, 0000401f, 0000301f}}
cycle: 389
Target memA: Socket_Req{RD, 004, 00003020, 00000000}}
cycle: 390
Target memA: Socket_Req{RD, 004, 00003021, 00000000}}
cycle: 391
Target memA: Socket_Req{RD, 004, 00003022, 00000000}}
cycle: 392
cycle: 393
Target memA: Socket_Req{WR, 007, 00006015, 00004015}}
cycle: 394
cycle: 395
Target memA: Socket_Req{WR, 005, 00004020, 00003020}}
cycle: 396
Target memA: Socket_Req{WR, 005, 00004021, 00003021}}
cycle: 397
Target memA: Socket_Req{WR, 005, 00004022, 00003022}}
cycle: 398
Target memA: Socket_Req{RD, 004, 00003023, 00000000}}
cycle: 399
Target memA: Socket_Req{RD, 004, 00003024, 00000000}}
cycle: 400
Target memA: Socket_Req{RD, 004, 00003025, 00000000}}
cycle: 401
cycle: 402
Target memA: Socket_Req{RD, 006, 00004016, 00000000}}
cycle: 403
cycle: 404
Target memA: Socket_Req{WR, 005, 00004023, 00003023}}
cycle: 405
Target memA: Socket_Req{WR, 005, 00004024, 00003024}}
cycle: 406
Target memA: Socket_Req{WR, 005, 00004025, 00003025}}
cycle: 407
Target memA: Socket_Req{RD, 004, 00003026, 00000000}}
cycle: 408
Target memA: Socket_Req{RD, 004, 00003027, 00000000}}
cycle: 409
Target memA: Socket_Req{WR, 007, 00006016, 00004016}}
cycle: 410
cycle: 411
Target memA: Socket_Req{RD, 006, 00004017, 00000000}}
cycle: 412
Target memA: Socket_Req{WR, 005, 00004026, 00003026}}
cycle: 413
Target memA: Socket_Req{WR, 005, 00004027, 00003027}}
cycle: 414
Target memA: Socket_Req{RD, 006, 00004018, 00000000}}
cycle: 415
Target memA: Socket_Req{WR, 007, 00006017, 00004017}}
cycle: 416
Target memA: Socket_Req{RD, 006, 00004019, 00000000}}
cycle: 417
Channel 2 is complete.
Target memA: Socket_Req{RD, 006, 0000401a, 00000000}}
cycle: 418
Target memA: Socket_Req{WR, 007, 00006018, 00004018}}
cycle: 419
cycle: 420
Target memA: Socket_Req{RD, 006, 0000401b, 00000000}}
cycle: 421
Target memA: Socket_Req{WR, 007, 00006019, 00004019}}
cycle: 422
Target memA: Socket_Req{WR, 007, 0000601a, 0000401a}}
cycle: 423
Target memA: Socket_Req{RD, 006, 0000401c, 00000000}}
cycle: 424
Target memA: Socket_Req{WR, 007, 0000601b, 0000401b}}
cycle: 425
Target memA: Socket_Req{RD, 006, 0000401d, 00000000}}
cycle: 426
Target memA: Socket_Req{RD, 006, 0000401e, 00000000}}
cycle: 427
Target memA: Socket_Req{WR, 007, 0000601c, 0000401c}}
cycle: 428
cycle: 429
Target memA: Socket_Req{RD, 006, 0000401f, 00000000}}
cycle: 430
Target memA: Socket_Req{WR, 007, 0000601d, 0000401d}}
cycle: 431
Target memA: Socket_Req{WR, 007, 0000601e, 0000401e}}
cycle: 432
Target memA: Socket_Req{RD, 006, 00004020, 00000000}}
cycle: 433
Target memA: Socket_Req{WR, 007, 0000601f, 0000401f}}
cycle: 434
Target memA: Socket_Req{RD, 006, 00004021, 00000000}}
cycle: 435
Target memA: Socket_Req{RD, 006, 00004022, 00000000}}
cycle: 436
Target memA: Socket_Req{WR, 007, 00006020, 00004020}}
cycle: 437
cycle: 438
Target memA: Socket_Req{RD, 006, 00004023, 00000000}}
cycle: 439
Target memA: Socket_Req{WR, 007, 00006021, 00004021}}
cycle: 440
Target memA: Socket_Req{WR, 007, 00006022, 00004022}}
cycle: 441
Target memA: Socket_Req{RD, 006, 00004024, 00000000}}
cycle: 442
Target memA: Socket_Req{WR, 007, 00006023, 00004023}}
cycle: 443
Target memA: Socket_Req{RD, 006, 00004025, 00000000}}
cycle: 444
Target memA: Socket_Req{RD, 006, 00004026, 00000000}}
cycle: 445
Target memA: Socket_Req{WR, 007, 00006024, 00004024}}
cycle: 446
cycle: 447
Target memA: Socket_Req{RD, 006, 00004027, 00000000}}
cycle: 448
Target memA: Socket_Req{WR, 007, 00006025, 00004025}}
cycle: 449
Target memA: Socket_Req{WR, 007, 00006026, 00004026}}
cycle: 450
cycle: 451
Target memA: Socket_Req{WR, 007, 00006027, 00004027}}
cycle: 452
cycle: 453
cycle: 454
cycle: 455
Channel 3 is complete.
cycle: 456
All channels finished
cycle: 457
